Lines Matching +full:pinmux +full:-
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 BayLibre, SAS.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/mt8365-pinfunc.h>
19 compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
26 stdout-path = "serial0:921600n8";
31 compatible = "linaro,optee-tz";
36 gpio-keys {
37 compatible = "gpio-keys";
38 pinctrl-names = "default";
39 pinctrl-0 = <&gpio_keys>;
41 key-volume-up {
45 wakeup-source;
46 debounce-interval = <15>;
55 usb_otg_vbus: regulator-0 {
56 compatible = "regulator-fixed";
57 regulator-name = "otg_vbus";
58 regulator-min-microvolt = <5000000>;
59 regulator-max-microvolt = <5000000>;
61 enable-active-high;
64 reserved-memory {
65 #address-cells = <2>;
66 #size-cells = <2>;
71 no-map;
75 /* 12 MiB reserved for OP-TEE (BL32)
76 * +-----------------------+ 0x43e0_0000
78 * +-----------------------+ 0x43c0_0000
80 * + TZDRAM +--------------+ 0x4340_0000
82 * +-----------------------+ 0x4320_0000
85 no-map;
92 proc-supply = <&mt6357_vproc_reg>;
93 sram-supply = <&mt6357_vsram_proc_reg>;
97 proc-supply = <&mt6357_vproc_reg>;
98 sram-supply = <&mt6357_vsram_proc_reg>;
102 proc-supply = <&mt6357_vproc_reg>;
103 sram-supply = <&mt6357_vsram_proc_reg>;
107 proc-supply = <&mt6357_vproc_reg>;
108 sram-supply = <&mt6357_vsram_proc_reg>;
112 pinctrl-0 = <ðernet_pins>;
113 pinctrl-names = "default";
114 phy-handle = <ð_phy>;
115 phy-mode = "rmii";
125 #address-cells = <1>;
126 #size-cells = <0>;
128 eth_phy: ethernet-phy@0 {
135 clock-frequency = <100000>;
136 pinctrl-0 = <&i2c0_pins>;
137 pinctrl-names = "default";
142 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
143 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
144 bus-width = <8>;
145 cap-mmc-highspeed;
146 cap-mmc-hw-reset;
147 hs400-ds-delay = <0x12012>;
148 max-frequency = <200000000>;
149 mmc-hs200-1_8v;
150 mmc-hs400-1_8v;
151 no-sd;
152 no-sdio;
153 non-removable;
154 pinctrl-0 = <&mmc0_default_pins>;
155 pinctrl-1 = <&mmc0_uhs_pins>;
156 pinctrl-names = "default", "state_uhs";
157 vmmc-supply = <&mt6357_vemc_reg>;
158 vqmmc-supply = <&mt6357_vio18_reg>;
163 bus-width = <4>;
164 cap-sd-highspeed;
165 cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
166 max-frequency = <200000000>;
167 pinctrl-0 = <&mmc1_default_pins>;
168 pinctrl-1 = <&mmc1_uhs_pins>;
169 pinctrl-names = "default", "state_uhs";
170 sd-uhs-sdr104;
171 sd-uhs-sdr50;
172 vmmc-supply = <&mt6357_vmch_reg>;
173 vqmmc-supply = <&mt6357_vmc_reg>;
178 interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
179 interrupt-controller;
180 #interrupt-cells = <2>;
184 ethernet_pins: ethernet-pins {
186 pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
190 pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
209 gpio_keys: gpio-keys-pins {
211 pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
212 bias-pull-up;
213 input-enable;
217 i2c0_pins: i2c0-pins {
219 pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
221 bias-pull-up;
225 mmc0_default_pins: mmc0-default-pins {
226 clk-pins {
227 pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
228 bias-pull-down;
231 cmd-dat-pins {
232 pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
241 input-enable;
242 bias-pull-up;
245 rst-pins {
246 pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
247 bias-pull-up;
251 mmc0_uhs_pins: mmc0-uhs-pins {
252 clk-pins {
253 pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
254 drive-strength = <MTK_DRIVE_10mA>;
255 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
258 cmd-dat-pins {
259 pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
268 input-enable;
269 drive-strength = <MTK_DRIVE_10mA>;
270 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
273 ds-pins {
274 pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
275 drive-strength = <MTK_DRIVE_10mA>;
276 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
279 rst-pins {
280 pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
281 drive-strength = <MTK_DRIVE_10mA>;
282 bias-pull-up;
286 mmc1_default_pins: mmc1-default-pins {
287 cd-pins {
288 pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
289 bias-pull-up;
292 clk-pins {
293 pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
294 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
297 cmd-dat-pins {
298 pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
303 input-enable;
304 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
308 mmc1_uhs_pins: mmc1-uhs-pins {
309 clk-pins {
310 pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
311 drive-strength = <MTK_DRIVE_8mA>;
312 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
315 cmd-dat-pins {
316 pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
321 input-enable;
322 drive-strength = <MTK_DRIVE_6mA>;
323 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
327 uart0_pins: uart0-pins {
329 pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
334 uart1_pins: uart1-pins {
336 pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
341 uart2_pins: uart2-pins {
343 pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
348 usb_pins: usb-pins {
349 id-pins {
350 pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
351 input-enable;
352 bias-pull-up;
355 usb0-vbus-pins {
356 pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
357 output-high;
360 usb1-vbus-pins {
361 pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
362 output-high;
366 pwm_pins: pwm-pins {
368 pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
375 pinctrl-0 = <&pwm_pins>;
376 pinctrl-names = "default";
382 maximum-speed = "high-speed";
383 pinctrl-0 = <&usb_pins>;
384 pinctrl-names = "default";
385 usb-role-switch;
386 vusb33-supply = <&mt6357_vusb33_reg>;
390 compatible = "gpio-usb-b-connector", "usb-b-connector";
391 id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
393 vbus-supply = <&usb_otg_vbus>;
398 vusb33-supply = <&mt6357_vusb33_reg>;
403 pinctrl-0 = <&uart0_pins>;
404 pinctrl-names = "default";
409 pinctrl-0 = <&uart1_pins>;
410 pinctrl-names = "default";
415 pinctrl-0 = <&uart2_pins>;
416 pinctrl-names = "default";