Lines Matching full:vdosys1
703 <&vdosys1 CLK_VDO1_SMI_LARB2>,
704 <&vdosys1 CLK_VDO1_SMI_LARB3>,
705 <&vdosys1 CLK_VDO1_GALS>;
706 clock-names = "vdosys1", "vdosys1-0",
707 "vdosys1-1", "vdosys1-2";
3296 vdosys1: syscon@1c100000 { label
3297 compatible = "mediatek,mt8195-vdosys1", "syscon";
3337 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
3348 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
3349 <&vdosys1 CLK_VDO1_SMI_LARB2>,
3350 <&vdosys1 CLK_VDO1_GALS>;
3360 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
3361 <&vdosys1 CLK_VDO1_GALS>,
3371 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
3382 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
3393 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
3404 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
3415 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
3426 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
3437 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
3448 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
3459 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
3460 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
3465 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
3472 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
3473 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
3478 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
3485 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
3486 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
3491 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
3498 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
3499 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
3504 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
3511 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
3512 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
3517 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
3525 clocks = <&vdosys1 CLK_VDO1_DPINTF>,
3526 <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
3550 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
3551 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
3552 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
3553 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
3554 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
3555 <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
3556 <&vdosys1 CLK_VDO1_26M_SLOW>,
3557 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
3558 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
3559 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
3560 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
3561 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
3571 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
3572 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
3573 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
3574 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
3575 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;