Lines Matching +full:mt8192 +full:- +full:vdecsys
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
16 #include <dt-bindings/reset/mt8195-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
39 vdo1-rdma0 = &vdo1_rdma0;
40 vdo1-rdma1 = &vdo1_rdma1;
41 vdo1-rdma2 = &vdo1_rdma2;
42 vdo1-rdma3 = &vdo1_rdma3;
43 vdo1-rdma4 = &vdo1_rdma4;
44 vdo1-rdma5 = &vdo1_rdma5;
45 vdo1-rdma6 = &vdo1_rdma6;
46 vdo1-rdma7 = &vdo1_rdma7;
50 #address-cells = <1>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a55";
57 enable-method = "psci";
58 performance-domains = <&performance 0>;
59 clock-frequency = <1701000000>;
60 capacity-dmips-mhz = <308>;
61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
62 i-cache-size = <32768>;
63 i-cache-line-size = <64>;
64 i-cache-sets = <128>;
65 d-cache-size = <32768>;
66 d-cache-line-size = <64>;
67 d-cache-sets = <128>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
74 compatible = "arm,cortex-a55";
76 enable-method = "psci";
77 performance-domains = <&performance 0>;
78 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
81 i-cache-size = <32768>;
82 i-cache-line-size = <64>;
83 i-cache-sets = <128>;
84 d-cache-size = <32768>;
85 d-cache-line-size = <64>;
86 d-cache-sets = <128>;
87 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>;
93 compatible = "arm,cortex-a55";
95 enable-method = "psci";
96 performance-domains = <&performance 0>;
97 clock-frequency = <1701000000>;
98 capacity-dmips-mhz = <308>;
99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
100 i-cache-size = <32768>;
101 i-cache-line-size = <64>;
102 i-cache-sets = <128>;
103 d-cache-size = <32768>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 next-level-cache = <&l2_0>;
107 #cooling-cells = <2>;
112 compatible = "arm,cortex-a55";
114 enable-method = "psci";
115 performance-domains = <&performance 0>;
116 clock-frequency = <1701000000>;
117 capacity-dmips-mhz = <308>;
118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
119 i-cache-size = <32768>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <128>;
122 d-cache-size = <32768>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&l2_0>;
126 #cooling-cells = <2>;
131 compatible = "arm,cortex-a78";
133 enable-method = "psci";
134 performance-domains = <&performance 1>;
135 clock-frequency = <2171000000>;
136 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
138 i-cache-size = <65536>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <256>;
141 d-cache-size = <65536>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <256>;
144 next-level-cache = <&l2_1>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a78";
152 enable-method = "psci";
153 performance-domains = <&performance 1>;
154 clock-frequency = <2171000000>;
155 capacity-dmips-mhz = <1024>;
156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
157 i-cache-size = <65536>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <256>;
160 d-cache-size = <65536>;
161 d-cache-line-size = <64>;
162 d-cache-sets = <256>;
163 next-level-cache = <&l2_1>;
164 #cooling-cells = <2>;
169 compatible = "arm,cortex-a78";
171 enable-method = "psci";
172 performance-domains = <&performance 1>;
173 clock-frequency = <2171000000>;
174 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
176 i-cache-size = <65536>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <65536>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&l2_1>;
183 #cooling-cells = <2>;
188 compatible = "arm,cortex-a78";
190 enable-method = "psci";
191 performance-domains = <&performance 1>;
192 clock-frequency = <2171000000>;
193 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
195 i-cache-size = <65536>;
196 i-cache-line-size = <64>;
197 i-cache-sets = <256>;
198 d-cache-size = <65536>;
199 d-cache-line-size = <64>;
200 d-cache-sets = <256>;
201 next-level-cache = <&l2_1>;
202 #cooling-cells = <2>;
205 cpu-map {
241 idle-states {
242 entry-method = "psci";
244 cpu_ret_l: cpu-retention-l {
245 compatible = "arm,idle-state";
246 arm,psci-suspend-param = <0x00010001>;
247 local-timer-stop;
248 entry-latency-us = <50>;
249 exit-latency-us = <95>;
250 min-residency-us = <580>;
253 cpu_ret_b: cpu-retention-b {
254 compatible = "arm,idle-state";
255 arm,psci-suspend-param = <0x00010001>;
256 local-timer-stop;
257 entry-latency-us = <45>;
258 exit-latency-us = <140>;
259 min-residency-us = <740>;
262 cpu_off_l: cpu-off-l {
263 compatible = "arm,idle-state";
264 arm,psci-suspend-param = <0x01010002>;
265 local-timer-stop;
266 entry-latency-us = <55>;
267 exit-latency-us = <155>;
268 min-residency-us = <840>;
271 cpu_off_b: cpu-off-b {
272 compatible = "arm,idle-state";
273 arm,psci-suspend-param = <0x01010002>;
274 local-timer-stop;
275 entry-latency-us = <50>;
276 exit-latency-us = <200>;
277 min-residency-us = <1000>;
281 l2_0: l2-cache0 {
283 cache-level = <2>;
284 cache-size = <131072>;
285 cache-line-size = <64>;
286 cache-sets = <512>;
287 next-level-cache = <&l3_0>;
288 cache-unified;
291 l2_1: l2-cache1 {
293 cache-level = <2>;
294 cache-size = <262144>;
295 cache-line-size = <64>;
296 cache-sets = <512>;
297 next-level-cache = <&l3_0>;
298 cache-unified;
301 l3_0: l3-cache {
303 cache-level = <3>;
304 cache-size = <2097152>;
305 cache-line-size = <64>;
306 cache-sets = <2048>;
307 cache-unified;
311 dsu-pmu {
312 compatible = "arm,dsu-pmu";
319 dmic_codec: dmic-codec {
320 compatible = "dmic-codec";
321 num-channels = <2>;
322 wakeup-delay-ms = <50>;
325 sound: mt8195-sound {
330 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clock";
332 #clock-cells = <0>;
334 clock-div = <2>;
335 clock-mult = <1>;
336 clock-output-names = "clk13m";
339 clk26m: oscillator-26m {
340 compatible = "fixed-clock";
341 #clock-cells = <0>;
342 clock-frequency = <26000000>;
343 clock-output-names = "clk26m";
346 clk32k: oscillator-32k {
347 compatible = "fixed-clock";
348 #clock-cells = <0>;
349 clock-frequency = <32768>;
350 clock-output-names = "clk32k";
353 performance: performance-controller@11bc10 {
354 compatible = "mediatek,cpufreq-hw";
356 #performance-domain-cells = <1>;
359 gpu_opp_table: opp-table-gpu {
360 compatible = "operating-points-v2";
361 opp-shared;
363 opp-390000000 {
364 opp-hz = /bits/ 64 <390000000>;
365 opp-microvolt = <625000>;
367 opp-410000000 {
368 opp-hz = /bits/ 64 <410000000>;
369 opp-microvolt = <631250>;
371 opp-431000000 {
372 opp-hz = /bits/ 64 <431000000>;
373 opp-microvolt = <631250>;
375 opp-473000000 {
376 opp-hz = /bits/ 64 <473000000>;
377 opp-microvolt = <637500>;
379 opp-515000000 {
380 opp-hz = /bits/ 64 <515000000>;
381 opp-microvolt = <637500>;
383 opp-556000000 {
384 opp-hz = /bits/ 64 <556000000>;
385 opp-microvolt = <643750>;
387 opp-598000000 {
388 opp-hz = /bits/ 64 <598000000>;
389 opp-microvolt = <650000>;
391 opp-640000000 {
392 opp-hz = /bits/ 64 <640000000>;
393 opp-microvolt = <650000>;
395 opp-670000000 {
396 opp-hz = /bits/ 64 <670000000>;
397 opp-microvolt = <662500>;
399 opp-700000000 {
400 opp-hz = /bits/ 64 <700000000>;
401 opp-microvolt = <675000>;
403 opp-730000000 {
404 opp-hz = /bits/ 64 <730000000>;
405 opp-microvolt = <687500>;
407 opp-760000000 {
408 opp-hz = /bits/ 64 <760000000>;
409 opp-microvolt = <700000>;
411 opp-790000000 {
412 opp-hz = /bits/ 64 <790000000>;
413 opp-microvolt = <712500>;
415 opp-820000000 {
416 opp-hz = /bits/ 64 <820000000>;
417 opp-microvolt = <725000>;
419 opp-850000000 {
420 opp-hz = /bits/ 64 <850000000>;
421 opp-microvolt = <737500>;
423 opp-880000000 {
424 opp-hz = /bits/ 64 <880000000>;
425 opp-microvolt = <750000>;
429 pmu-a55 {
430 compatible = "arm,cortex-a55-pmu";
431 interrupt-parent = <&gic>;
435 pmu-a78 {
436 compatible = "arm,cortex-a78-pmu";
437 interrupt-parent = <&gic>;
442 compatible = "arm,psci-1.0";
447 compatible = "arm,armv8-timer";
448 interrupt-parent = <&gic>;
456 #address-cells = <2>;
457 #size-cells = <2>;
458 compatible = "simple-bus";
460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
462 gic: interrupt-controller@c000000 {
463 compatible = "arm,gic-v3";
464 #interrupt-cells = <4>;
465 #redistributor-regions = <1>;
466 interrupt-parent = <&gic>;
467 interrupt-controller;
472 ppi-partitions {
473 ppi_cluster0: interrupt-partition-0 {
477 ppi_cluster1: interrupt-partition-1 {
484 compatible = "mediatek,mt8195-topckgen", "syscon";
486 #clock-cells = <1>;
490 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
492 #clock-cells = <1>;
493 #reset-cells = <1>;
497 compatible = "mediatek,mt8195-pericfg", "syscon";
499 #clock-cells = <1>;
503 compatible = "mediatek,mt8195-pinctrl";
512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
515 gpio-controller;
516 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0 0 144>;
518 interrupt-controller;
520 #interrupt-cells = <2>;
524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
528 spm: power-controller {
529 compatible = "mediatek,mt8195-power-controller";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 #power-domain-cells = <1>;
535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <1>;
541 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 {
545 clock-names = "mfg", "alt";
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #power-domain-cells = <1>;
551 power-domain@MT8195_POWER_DOMAIN_MFG2 {
553 #power-domain-cells = <0>;
556 power-domain@MT8195_POWER_DOMAIN_MFG3 {
558 #power-domain-cells = <0>;
561 power-domain@MT8195_POWER_DOMAIN_MFG4 {
563 #power-domain-cells = <0>;
566 power-domain@MT8195_POWER_DOMAIN_MFG5 {
568 #power-domain-cells = <0>;
571 power-domain@MT8195_POWER_DOMAIN_MFG6 {
573 #power-domain-cells = <0>;
578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 "vppsys0-18";
616 #address-cells = <1>;
617 #size-cells = <0>;
618 #power-domain-cells = <1>;
620 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
622 clocks = <&vdecsys CLK_VDEC_LARB1>;
623 clock-names = "vdec1-0";
625 #power-domain-cells = <0>;
628 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
631 clock-names = "venc1-larb";
633 #power-domain-cells = <0>;
636 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
645 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
646 "vdosys0-2", "vdosys0-3",
647 "vdosys0-4", "vdosys0-5";
649 #address-cells = <1>;
650 #size-cells = <0>;
651 #power-domain-cells = <1>;
653 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
658 clock-names = "vppsys1", "vppsys1-0",
659 "vppsys1-1";
661 #power-domain-cells = <0>;
664 power-domain@MT8195_POWER_DOMAIN_WPESYS {
670 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
671 "wepsys-3";
673 #power-domain-cells = <0>;
676 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
679 clock-names = "vdec0-0";
681 #power-domain-cells = <0>;
684 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
687 clock-names = "vdec2-0";
689 #power-domain-cells = <0>;
692 power-domain@MT8195_POWER_DOMAIN_VENC {
695 clock-names = "venc0-larb";
697 #power-domain-cells = <0>;
700 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
706 clock-names = "vdosys1", "vdosys1-0",
707 "vdosys1-1", "vdosys1-2";
709 #address-cells = <1>;
710 #size-cells = <0>;
711 #power-domain-cells = <1>;
713 power-domain@MT8195_POWER_DOMAIN_DP_TX {
716 #power-domain-cells = <0>;
719 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
722 #power-domain-cells = <0>;
725 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
728 clock-names = "hdmi_tx";
729 #power-domain-cells = <0>;
733 power-domain@MT8195_POWER_DOMAIN_IMG {
737 clock-names = "img-0", "img-1";
739 #address-cells = <1>;
740 #size-cells = <0>;
741 #power-domain-cells = <1>;
743 power-domain@MT8195_POWER_DOMAIN_DIP {
745 #power-domain-cells = <0>;
748 power-domain@MT8195_POWER_DOMAIN_IPE {
753 clock-names = "ipe", "ipe-0", "ipe-1";
755 #power-domain-cells = <0>;
759 power-domain@MT8195_POWER_DOMAIN_CAM {
766 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
767 "cam-4";
769 #address-cells = <1>;
770 #size-cells = <0>;
771 #power-domain-cells = <1>;
773 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
775 #power-domain-cells = <0>;
778 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
780 #power-domain-cells = <0>;
783 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
785 #power-domain-cells = <0>;
791 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
794 #power-domain-cells = <0>;
797 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
800 #power-domain-cells = <0>;
803 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
805 #power-domain-cells = <0>;
808 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
810 #power-domain-cells = <0>;
813 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
817 clock-names = "csi_rx_top", "csi_rx_top1";
818 #power-domain-cells = <0>;
821 power-domain@MT8195_POWER_DOMAIN_ETHER {
824 clock-names = "ether";
825 #power-domain-cells = <0>;
828 power-domain@MT8195_POWER_DOMAIN_ADSP {
832 clock-names = "adsp", "adsp1";
833 #address-cells = <1>;
834 #size-cells = <0>;
836 #power-domain-cells = <1>;
838 power-domain@MT8195_POWER_DOMAIN_AUDIO {
844 clock-names = "audio", "audio1", "audio2",
847 #power-domain-cells = <0>;
854 compatible = "mediatek,mt8195-wdt";
855 mediatek,disable-extrst;
857 #reset-cells = <1>;
861 compatible = "mediatek,mt8195-apmixedsys", "syscon";
863 #clock-cells = <1>;
867 compatible = "mediatek,mt8195-timer",
868 "mediatek,mt6765-timer";
875 compatible = "mediatek,mt8195-pwrap", "syscon";
877 reg-names = "pwrap";
881 clock-names = "spi", "wrap";
882 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
883 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
887 compatible = "mediatek,mt8195-spmi";
890 reg-names = "pmif", "spmimst";
894 clock-names = "pmif_sys_ck",
897 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
898 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
901 iommu_infra: infra-iommu@10315000 {
902 compatible = "mediatek,mt8195-iommu-infra";
909 #iommu-cells = <1>;
913 compatible = "mediatek,mt8195-gce";
916 #mbox-cells = <2>;
921 compatible = "mediatek,mt8195-gce";
924 #mbox-cells = <2>;
929 compatible = "mediatek,mt8195-scp";
933 reg-names = "sram", "cfg", "l1tcm";
938 scp_adsp: clock-controller@10720000 {
939 compatible = "mediatek,mt8195-scp_adsp";
941 #clock-cells = <1>;
945 compatible = "mediatek,mt8195-dsp";
948 reg-names = "cfg", "sram";
955 clock-names = "adsp_sel",
961 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
962 mbox-names = "rx", "tx";
968 compatible = "mediatek,mt8195-adsp-mbox";
969 #mbox-cells = <0>;
975 compatible = "mediatek,mt8195-adsp-mbox";
976 #mbox-cells = <0>;
981 afe: mt8195-afe-pcm@10890000 {
982 compatible = "mediatek,mt8195-audio";
985 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
988 reset-names = "audiosys";
1008 clock-names = "clk26m",
1031 compatible = "mediatek,mt8195-uart",
1032 "mediatek,mt6577-uart";
1036 clock-names = "baud", "bus";
1041 compatible = "mediatek,mt8195-uart",
1042 "mediatek,mt6577-uart";
1046 clock-names = "baud", "bus";
1051 compatible = "mediatek,mt8195-uart",
1052 "mediatek,mt6577-uart";
1056 clock-names = "baud", "bus";
1061 compatible = "mediatek,mt8195-uart",
1062 "mediatek,mt6577-uart";
1066 clock-names = "baud", "bus";
1071 compatible = "mediatek,mt8195-uart",
1072 "mediatek,mt6577-uart";
1076 clock-names = "baud", "bus";
1081 compatible = "mediatek,mt8195-uart",
1082 "mediatek,mt6577-uart";
1086 clock-names = "baud", "bus";
1091 compatible = "mediatek,mt8195-auxadc",
1092 "mediatek,mt8173-auxadc";
1095 clock-names = "main";
1096 #io-channel-cells = <1>;
1101 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1103 #clock-cells = <1>;
1107 compatible = "mediatek,mt8195-spi",
1108 "mediatek,mt6765-spi";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1116 clock-names = "parent-clk", "sel-clk", "spi-clk";
1120 lvts_ap: thermal-sensor@1100b000 {
1121 compatible = "mediatek,mt8195-lvts-ap";
1126 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1127 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1128 #thermal-sensor-cells = <1>;
1132 compatible = "mediatek,mt8195-svs";
1136 clock-names = "main";
1137 nvmem-cells = <&svs_calib_data &lvts_efuse_data1>;
1138 nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
1140 reset-names = "svs_rst";
1144 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1147 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1148 #pwm-cells = <2>;
1151 clock-names = "main", "mm";
1156 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1159 #pwm-cells = <2>;
1162 clock-names = "main", "mm";
1167 compatible = "mediatek,mt8195-spi",
1168 "mediatek,mt6765-spi";
1169 #address-cells = <1>;
1170 #size-cells = <0>;
1176 clock-names = "parent-clk", "sel-clk", "spi-clk";
1181 compatible = "mediatek,mt8195-spi",
1182 "mediatek,mt6765-spi";
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1190 clock-names = "parent-clk", "sel-clk", "spi-clk";
1195 compatible = "mediatek,mt8195-spi",
1196 "mediatek,mt6765-spi";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1204 clock-names = "parent-clk", "sel-clk", "spi-clk";
1209 compatible = "mediatek,mt8195-spi",
1210 "mediatek,mt6765-spi";
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1218 clock-names = "parent-clk", "sel-clk", "spi-clk";
1223 compatible = "mediatek,mt8195-spi",
1224 "mediatek,mt6765-spi";
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1232 clock-names = "parent-clk", "sel-clk", "spi-clk";
1237 compatible = "mediatek,mt8195-spi-slave";
1241 clock-names = "spi";
1242 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1243 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1248 compatible = "mediatek,mt8195-spi-slave";
1252 clock-names = "spi";
1253 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1254 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1259 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1262 interrupt-names = "macirq";
1263 clock-names = "axi",
1275 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1278 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1281 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1283 snps,axi-config = <&stmmac_axi_setup>;
1284 snps,mtl-rx-config = <&mtl_rx_setup>;
1285 snps,mtl-tx-config = <&mtl_tx_setup>;
1288 snps,clk-csr = <0>;
1292 compatible = "snps,dwmac-mdio";
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1297 stmmac_axi_setup: stmmac-axi-config {
1303 mtl_rx_setup: rx-queues-config {
1304 snps,rx-queues-to-use = <4>;
1305 snps,rx-sched-sp;
1307 snps,dcb-algorithm;
1308 snps,map-to-dma-channel = <0x0>;
1311 snps,dcb-algorithm;
1312 snps,map-to-dma-channel = <0x0>;
1315 snps,dcb-algorithm;
1316 snps,map-to-dma-channel = <0x0>;
1319 snps,dcb-algorithm;
1320 snps,map-to-dma-channel = <0x0>;
1324 mtl_tx_setup: tx-queues-config {
1325 snps,tx-queues-to-use = <4>;
1326 snps,tx-sched-wrr;
1329 snps,dcb-algorithm;
1334 snps,dcb-algorithm;
1339 snps,dcb-algorithm;
1344 snps,dcb-algorithm;
1351 compatible = "mediatek,mt8195-xhci",
1352 "mediatek,mtk-xhci";
1355 reg-names = "mac", "ippc";
1359 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1361 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1368 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1370 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1371 wakeup-source;
1376 compatible = "mediatek,mt8195-mmc",
1377 "mediatek,mt8183-mmc";
1384 clock-names = "source", "hclk", "source_cg";
1389 compatible = "mediatek,mt8195-mmc",
1390 "mediatek,mt8183-mmc";
1397 clock-names = "source", "hclk", "source_cg";
1398 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1399 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1404 compatible = "mediatek,mt8195-mmc",
1405 "mediatek,mt8183-mmc";
1412 clock-names = "source", "hclk", "source_cg";
1413 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1414 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1418 lvts_mcu: thermal-sensor@11278000 {
1419 compatible = "mediatek,mt8195-lvts-mcu";
1424 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1425 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1426 #thermal-sensor-cells = <1>;
1430 compatible = "mediatek,mt8195-xhci",
1431 "mediatek,mtk-xhci";
1434 reg-names = "mac", "ippc";
1437 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1439 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1446 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1448 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1449 wakeup-source;
1454 compatible = "mediatek,mt8195-xhci",
1455 "mediatek,mtk-xhci";
1458 reg-names = "mac", "ippc";
1461 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1463 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1470 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1472 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1473 wakeup-source;
1478 compatible = "mediatek,mt8195-xhci",
1479 "mediatek,mtk-xhci";
1482 reg-names = "mac", "ippc";
1485 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1487 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1494 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1496 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1497 wakeup-source;
1502 compatible = "mediatek,mt8195-pcie",
1503 "mediatek,mt8192-pcie";
1505 #address-cells = <3>;
1506 #size-cells = <2>;
1508 reg-names = "pcie-mac";
1510 bus-range = <0x00 0xff>;
1516 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1517 iommu-map-mask = <0x0>;
1525 clock-names = "pl_250m", "tl_26m", "tl_96m",
1527 assigned-clocks = <&topckgen CLK_TOP_TL>;
1528 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1531 phy-names = "pcie-phy";
1533 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1536 reset-names = "mac";
1538 #interrupt-cells = <1>;
1539 interrupt-map-mask = <0 0 0 7>;
1540 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1546 pcie_intc0: interrupt-controller {
1547 interrupt-controller;
1548 #address-cells = <0>;
1549 #interrupt-cells = <1>;
1554 compatible = "mediatek,mt8195-pcie",
1555 "mediatek,mt8192-pcie";
1557 #address-cells = <3>;
1558 #size-cells = <2>;
1560 reg-names = "pcie-mac";
1562 bus-range = <0x00 0xff>;
1568 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1569 iommu-map-mask = <0x0>;
1578 clock-names = "pl_250m", "tl_26m", "tl_96m",
1580 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1581 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1584 phy-names = "pcie-phy";
1585 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1588 reset-names = "mac";
1590 #interrupt-cells = <1>;
1591 interrupt-map-mask = <0 0 0 7>;
1592 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1598 pcie_intc1: interrupt-controller {
1599 interrupt-controller;
1600 #address-cells = <0>;
1601 #interrupt-cells = <1>;
1606 compatible = "mediatek,mt8195-nor",
1607 "mediatek,mt8173-nor";
1613 clock-names = "spi", "sf", "axi";
1614 #address-cells = <1>;
1615 #size-cells = <0>;
1620 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1622 #address-cells = <1>;
1623 #size-cells = <1>;
1624 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1628 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1632 u3_intr_p0: usb3-intr@185 {
1636 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1640 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1644 comb_intr_p1: usb3-intr@187 {
1648 u2_intr_p0: usb2-intr-p0@188,1 {
1652 u2_intr_p1: usb2-intr-p1@188,2 {
1656 u2_intr_p2: usb2-intr-p2@189,1 {
1660 u2_intr_p3: usb2-intr-p3@189,2 {
1664 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1668 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1672 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1676 pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1680 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1684 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1688 pciephy_glb_intr: pciephy-glb-intr@193 {
1692 dp_calibration: dp-data@1ac {
1695 lvts_efuse_data1: lvts1-calib@1bc {
1698 lvts_efuse_data2: lvts2-calib@1d0 {
1701 svs_calib_data: svs-calib@580 {
1706 u3phy2: t-phy@11c40000 {
1707 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1708 #address-cells = <1>;
1709 #size-cells = <1>;
1713 u2port2: usb-phy@0 {
1716 clock-names = "ref";
1717 #phy-cells = <1>;
1721 u3phy3: t-phy@11c50000 {
1722 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1723 #address-cells = <1>;
1724 #size-cells = <1>;
1728 u2port3: usb-phy@0 {
1731 clock-names = "ref";
1732 #phy-cells = <1>;
1736 mipi_tx0: dsi-phy@11c80000 {
1737 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1740 clock-output-names = "mipi_tx0_pll";
1741 #clock-cells = <0>;
1742 #phy-cells = <0>;
1746 mipi_tx1: dsi-phy@11c90000 {
1747 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1750 clock-output-names = "mipi_tx1_pll";
1751 #clock-cells = <0>;
1752 #phy-cells = <0>;
1757 compatible = "mediatek,mt8195-i2c",
1758 "mediatek,mt8192-i2c";
1762 clock-div = <1>;
1765 clock-names = "main", "dma";
1766 #address-cells = <1>;
1767 #size-cells = <0>;
1772 compatible = "mediatek,mt8195-i2c",
1773 "mediatek,mt8192-i2c";
1777 clock-div = <1>;
1780 clock-names = "main", "dma";
1781 #address-cells = <1>;
1782 #size-cells = <0>;
1787 compatible = "mediatek,mt8195-i2c",
1788 "mediatek,mt8192-i2c";
1792 clock-div = <1>;
1795 clock-names = "main", "dma";
1796 #address-cells = <1>;
1797 #size-cells = <0>;
1801 imp_iic_wrap_s: clock-controller@11d03000 {
1802 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1804 #clock-cells = <1>;
1808 compatible = "mediatek,mt8195-i2c",
1809 "mediatek,mt8192-i2c";
1813 clock-div = <1>;
1816 clock-names = "main", "dma";
1817 #address-cells = <1>;
1818 #size-cells = <0>;
1823 compatible = "mediatek,mt8195-i2c",
1824 "mediatek,mt8192-i2c";
1828 clock-div = <1>;
1831 clock-names = "main", "dma";
1832 #address-cells = <1>;
1833 #size-cells = <0>;
1838 compatible = "mediatek,mt8195-i2c",
1839 "mediatek,mt8192-i2c";
1843 clock-div = <1>;
1846 clock-names = "main", "dma";
1847 #address-cells = <1>;
1848 #size-cells = <0>;
1853 compatible = "mediatek,mt8195-i2c",
1854 "mediatek,mt8192-i2c";
1858 clock-div = <1>;
1861 clock-names = "main", "dma";
1862 #address-cells = <1>;
1863 #size-cells = <0>;
1868 compatible = "mediatek,mt8195-i2c",
1869 "mediatek,mt8192-i2c";
1873 clock-div = <1>;
1876 clock-names = "main", "dma";
1877 #address-cells = <1>;
1878 #size-cells = <0>;
1882 imp_iic_wrap_w: clock-controller@11e05000 {
1883 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1885 #clock-cells = <1>;
1888 u3phy1: t-phy@11e30000 {
1889 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1890 #address-cells = <1>;
1891 #size-cells = <1>;
1893 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1896 u2port1: usb-phy@0 {
1900 clock-names = "ref", "da_ref";
1901 #phy-cells = <1>;
1904 u3port1: usb-phy@700 {
1908 clock-names = "ref", "da_ref";
1909 nvmem-cells = <&comb_intr_p1>,
1912 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1913 #phy-cells = <1>;
1917 u3phy0: t-phy@11e40000 {
1918 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1919 #address-cells = <1>;
1920 #size-cells = <1>;
1924 u2port0: usb-phy@0 {
1928 clock-names = "ref", "da_ref";
1929 #phy-cells = <1>;
1932 u3port0: usb-phy@700 {
1936 clock-names = "ref", "da_ref";
1937 nvmem-cells = <&u3_intr_p0>,
1940 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1941 #phy-cells = <1>;
1946 compatible = "mediatek,mt8195-pcie-phy";
1948 reg-names = "sif";
1949 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1953 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1957 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1958 #phy-cells = <0>;
1962 ufsphy: ufs-phy@11fa0000 {
1963 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1966 clock-names = "unipro", "mp";
1967 #phy-cells = <0>;
1972 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
1973 "arm,mali-valhall-jm";
1980 interrupt-names = "job", "mmu", "gpu";
1981 operating-points-v2 = <&gpu_opp_table>;
1982 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
1987 power-domain-names = "core0", "core1", "core2", "core3", "core4";
1991 mfgcfg: clock-controller@13fbf000 {
1992 compatible = "mediatek,mt8195-mfgcfg";
1994 #clock-cells = <1>;
1998 compatible = "mediatek,mt8195-vppsys0", "syscon";
2000 #clock-cells = <1>;
2003 dma-controller@14001000 {
2004 compatible = "mediatek,mt8195-mdp3-rdma";
2006 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2007 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2009 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2017 #dma-cells = <1>;
2021 compatible = "mediatek,mt8195-mdp3-fg";
2023 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
2028 compatible = "mediatek,mt8195-mdp3-stitch";
2030 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
2035 compatible = "mediatek,mt8195-mdp3-hdr";
2037 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
2042 compatible = "mediatek,mt8195-mdp3-aal";
2045 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
2047 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2051 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2053 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
2054 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
2060 compatible = "mediatek,mt8195-mdp3-tdshp";
2062 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
2067 compatible = "mediatek,mt8195-mdp3-color";
2070 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
2072 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2076 compatible = "mediatek,mt8195-mdp3-ovl";
2079 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
2081 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2086 compatible = "mediatek,mt8195-mdp3-padding";
2088 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
2090 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2094 compatible = "mediatek,mt8195-mdp3-tcc";
2096 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
2100 dma-controller@1400c000 {
2101 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2103 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
2104 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
2108 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2109 #dma-cells = <1>;
2113 compatible = "mediatek,mt8195-vpp-mutex";
2116 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
2118 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2122 compatible = "mediatek,mt8195-smi-sub-common";
2127 clock-names = "apb", "smi", "gals0";
2129 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2133 compatible = "mediatek,mt8195-smi-sub-common";
2138 clock-names = "apb", "smi", "gals0";
2140 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2144 compatible = "mediatek,mt8195-smi-common-vpp";
2150 clock-names = "apb", "smi", "gals0", "gals1";
2151 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2155 compatible = "mediatek,mt8195-smi-larb";
2157 mediatek,larb-id = <4>;
2161 clock-names = "apb", "smi";
2162 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2166 compatible = "mediatek,mt8195-iommu-vpp";
2174 clock-names = "bclk";
2175 #iommu-cells = <1>;
2176 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2179 wpesys: clock-controller@14e00000 {
2180 compatible = "mediatek,mt8195-wpesys";
2182 #clock-cells = <1>;
2185 wpesys_vpp0: clock-controller@14e02000 {
2186 compatible = "mediatek,mt8195-wpesys_vpp0";
2188 #clock-cells = <1>;
2191 wpesys_vpp1: clock-controller@14e03000 {
2192 compatible = "mediatek,mt8195-wpesys_vpp1";
2194 #clock-cells = <1>;
2198 compatible = "mediatek,mt8195-smi-larb";
2200 mediatek,larb-id = <7>;
2204 clock-names = "apb", "smi";
2205 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2209 compatible = "mediatek,mt8195-smi-larb";
2211 mediatek,larb-id = <8>;
2216 clock-names = "apb", "smi", "gals";
2217 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2221 compatible = "mediatek,mt8195-vppsys1", "syscon";
2223 #clock-cells = <1>;
2227 compatible = "mediatek,mt8195-vpp-mutex";
2230 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2232 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2236 compatible = "mediatek,mt8195-smi-larb";
2238 mediatek,larb-id = <5>;
2243 clock-names = "apb", "smi", "gals";
2244 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2248 compatible = "mediatek,mt8195-smi-larb";
2250 mediatek,larb-id = <6>;
2255 clock-names = "apb", "smi", "gals";
2256 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2260 compatible = "mediatek,mt8195-mdp3-split";
2262 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
2266 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2270 compatible = "mediatek,mt8195-mdp3-tcc";
2272 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
2276 dma-controller@14f08000 {
2277 compatible = "mediatek,mt8195-mdp3-rdma";
2279 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
2280 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
2284 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2285 #dma-cells = <1>;
2288 dma-controller@14f09000 {
2289 compatible = "mediatek,mt8195-mdp3-rdma";
2291 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
2292 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
2296 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2297 #dma-cells = <1>;
2300 dma-controller@14f0a000 {
2301 compatible = "mediatek,mt8195-mdp3-rdma";
2303 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
2304 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
2308 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2309 #dma-cells = <1>;
2313 compatible = "mediatek,mt8195-mdp3-fg";
2315 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
2320 compatible = "mediatek,mt8195-mdp3-fg";
2322 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
2327 compatible = "mediatek,mt8195-mdp3-fg";
2329 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
2334 compatible = "mediatek,mt8195-mdp3-hdr";
2336 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
2341 compatible = "mediatek,mt8195-mdp3-hdr";
2343 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
2348 compatible = "mediatek,mt8195-mdp3-hdr";
2350 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
2355 compatible = "mediatek,mt8195-mdp3-aal";
2358 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
2360 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2364 compatible = "mediatek,mt8195-mdp3-aal";
2367 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
2369 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2373 compatible = "mediatek,mt8195-mdp3-aal";
2376 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
2378 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2382 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2384 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
2385 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
2391 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2393 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
2394 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
2400 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2402 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
2403 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
2409 compatible = "mediatek,mt8195-mdp3-tdshp";
2411 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
2416 compatible = "mediatek,mt8195-mdp3-tdshp";
2418 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
2423 compatible = "mediatek,mt8195-mdp3-tdshp";
2425 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
2430 compatible = "mediatek,mt8195-mdp3-merge";
2432 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
2434 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2438 compatible = "mediatek,mt8195-mdp3-merge";
2440 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
2442 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2446 compatible = "mediatek,mt8195-mdp3-color";
2449 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
2451 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2455 compatible = "mediatek,mt8195-mdp3-color";
2457 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
2460 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2464 compatible = "mediatek,mt8195-mdp3-color";
2467 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
2469 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2473 compatible = "mediatek,mt8195-mdp3-ovl";
2476 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
2478 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2483 compatible = "mediatek,mt8195-mdp3-padding";
2485 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
2487 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2491 compatible = "mediatek,mt8195-mdp3-padding";
2493 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
2495 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2499 compatible = "mediatek,mt8195-mdp3-padding";
2501 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
2503 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2506 dma-controller@14f23000 {
2507 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2509 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
2510 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
2514 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2515 #dma-cells = <1>;
2518 dma-controller@14f24000 {
2519 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2521 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
2522 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
2526 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2527 #dma-cells = <1>;
2530 dma-controller@14f25000 {
2531 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2533 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
2534 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
2538 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2539 #dma-cells = <1>;
2542 imgsys: clock-controller@15000000 {
2543 compatible = "mediatek,mt8195-imgsys";
2545 #clock-cells = <1>;
2549 compatible = "mediatek,mt8195-smi-larb";
2551 mediatek,larb-id = <9>;
2556 clock-names = "apb", "smi", "gals";
2557 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2561 compatible = "mediatek,mt8195-smi-sub-common";
2566 clock-names = "apb", "smi", "gals0";
2568 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2572 compatible = "mediatek,mt8195-smi-sub-common";
2577 clock-names = "apb", "smi", "gals0";
2579 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2582 imgsys1_dip_top: clock-controller@15110000 {
2583 compatible = "mediatek,mt8195-imgsys1_dip_top";
2585 #clock-cells = <1>;
2589 compatible = "mediatek,mt8195-smi-larb";
2591 mediatek,larb-id = <10>;
2595 clock-names = "apb", "smi";
2596 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2599 imgsys1_dip_nr: clock-controller@15130000 {
2600 compatible = "mediatek,mt8195-imgsys1_dip_nr";
2602 #clock-cells = <1>;
2605 imgsys1_wpe: clock-controller@15220000 {
2606 compatible = "mediatek,mt8195-imgsys1_wpe";
2608 #clock-cells = <1>;
2612 compatible = "mediatek,mt8195-smi-larb";
2614 mediatek,larb-id = <11>;
2618 clock-names = "apb", "smi";
2619 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2622 ipesys: clock-controller@15330000 {
2623 compatible = "mediatek,mt8195-ipesys";
2625 #clock-cells = <1>;
2629 compatible = "mediatek,mt8195-smi-larb";
2631 mediatek,larb-id = <12>;
2635 clock-names = "apb", "smi";
2636 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2639 camsys: clock-controller@16000000 {
2640 compatible = "mediatek,mt8195-camsys";
2642 #clock-cells = <1>;
2646 compatible = "mediatek,mt8195-smi-larb";
2648 mediatek,larb-id = <13>;
2653 clock-names = "apb", "smi", "gals";
2654 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2658 compatible = "mediatek,mt8195-smi-larb";
2660 mediatek,larb-id = <14>;
2664 clock-names = "apb", "smi";
2665 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2669 compatible = "mediatek,mt8195-smi-sub-common";
2674 clock-names = "apb", "smi", "gals0";
2676 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2680 compatible = "mediatek,mt8195-smi-sub-common";
2685 clock-names = "apb", "smi", "gals0";
2687 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2691 compatible = "mediatek,mt8195-smi-larb";
2693 mediatek,larb-id = <16>;
2697 clock-names = "apb", "smi";
2698 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2702 compatible = "mediatek,mt8195-smi-larb";
2704 mediatek,larb-id = <17>;
2708 clock-names = "apb", "smi";
2709 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2713 compatible = "mediatek,mt8195-smi-larb";
2715 mediatek,larb-id = <27>;
2719 clock-names = "apb", "smi";
2720 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2724 compatible = "mediatek,mt8195-smi-larb";
2726 mediatek,larb-id = <28>;
2730 clock-names = "apb", "smi";
2731 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2734 camsys_rawa: clock-controller@1604f000 {
2735 compatible = "mediatek,mt8195-camsys_rawa";
2737 #clock-cells = <1>;
2740 camsys_yuva: clock-controller@1606f000 {
2741 compatible = "mediatek,mt8195-camsys_yuva";
2743 #clock-cells = <1>;
2746 camsys_rawb: clock-controller@1608f000 {
2747 compatible = "mediatek,mt8195-camsys_rawb";
2749 #clock-cells = <1>;
2752 camsys_yuvb: clock-controller@160af000 {
2753 compatible = "mediatek,mt8195-camsys_yuvb";
2755 #clock-cells = <1>;
2758 camsys_mraw: clock-controller@16140000 {
2759 compatible = "mediatek,mt8195-camsys_mraw";
2761 #clock-cells = <1>;
2765 compatible = "mediatek,mt8195-smi-larb";
2767 mediatek,larb-id = <25>;
2772 clock-names = "apb", "smi", "gals";
2773 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2777 compatible = "mediatek,mt8195-smi-larb";
2779 mediatek,larb-id = <26>;
2783 clock-names = "apb", "smi";
2784 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2788 ccusys: clock-controller@17200000 {
2789 compatible = "mediatek,mt8195-ccusys";
2791 #clock-cells = <1>;
2795 compatible = "mediatek,mt8195-smi-larb";
2797 mediatek,larb-id = <18>;
2801 clock-names = "apb", "smi";
2802 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2805 video-codec@18000000 {
2806 compatible = "mediatek,mt8195-vcodec-dec";
2809 #address-cells = <2>;
2810 #size-cells = <2>;
2815 video-codec@2000 {
2816 compatible = "mediatek,mtk-vcodec-lat-soc";
2824 clock-names = "sel", "vdec", "lat", "top";
2825 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2826 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2827 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2830 video-codec@10000 {
2831 compatible = "mediatek,mtk-vcodec-lat";
2844 clock-names = "sel", "vdec", "lat", "top";
2845 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2846 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2847 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2850 video-codec@25000 {
2851 compatible = "mediatek,mtk-vcodec-core";
2865 <&vdecsys CLK_VDEC_VDEC>,
2866 <&vdecsys CLK_VDEC_LAT>,
2868 clock-names = "sel", "vdec", "lat", "top";
2869 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2870 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2871 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2876 compatible = "mediatek,mt8195-smi-larb";
2878 mediatek,larb-id = <24>;
2882 clock-names = "apb", "smi";
2883 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2887 compatible = "mediatek,mt8195-smi-larb";
2889 mediatek,larb-id = <23>;
2893 clock-names = "apb", "smi";
2894 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2897 vdecsys_soc: clock-controller@1800f000 {
2898 compatible = "mediatek,mt8195-vdecsys_soc";
2900 #clock-cells = <1>;
2904 compatible = "mediatek,mt8195-smi-larb";
2906 mediatek,larb-id = <21>;
2908 clocks = <&vdecsys CLK_VDEC_LARB1>,
2909 <&vdecsys CLK_VDEC_LARB1>;
2910 clock-names = "apb", "smi";
2911 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2914 vdecsys: clock-controller@1802f000 {
2915 compatible = "mediatek,mt8195-vdecsys";
2917 #clock-cells = <1>;
2921 compatible = "mediatek,mt8195-smi-larb";
2923 mediatek,larb-id = <22>;
2927 clock-names = "apb", "smi";
2928 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2931 vdecsys_core1: clock-controller@1803f000 {
2932 compatible = "mediatek,mt8195-vdecsys_core1";
2934 #clock-cells = <1>;
2937 apusys_pll: clock-controller@190f3000 {
2938 compatible = "mediatek,mt8195-apusys_pll";
2940 #clock-cells = <1>;
2943 vencsys: clock-controller@1a000000 {
2944 compatible = "mediatek,mt8195-vencsys";
2946 #clock-cells = <1>;
2950 compatible = "mediatek,mt8195-smi-larb";
2952 mediatek,larb-id = <19>;
2956 clock-names = "apb", "smi";
2957 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2960 venc: video-codec@1a020000 {
2961 compatible = "mediatek,mt8195-vcodec-enc";
2975 clock-names = "venc_sel";
2976 assigned-clocks = <&topckgen CLK_TOP_VENC>;
2977 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2978 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2979 #address-cells = <2>;
2980 #size-cells = <2>;
2983 jpgdec-master {
2984 compatible = "mediatek,mt8195-jpgdec";
2985 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2992 #address-cells = <2>;
2993 #size-cells = <2>;
2997 compatible = "mediatek,mt8195-jpgdec-hw";
3007 clock-names = "jpgdec";
3008 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
3012 compatible = "mediatek,mt8195-jpgdec-hw";
3022 clock-names = "jpgdec";
3023 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3027 compatible = "mediatek,mt8195-jpgdec-hw";
3037 clock-names = "jpgdec";
3038 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
3042 vencsys_core1: clock-controller@1b000000 {
3043 compatible = "mediatek,mt8195-vencsys_core1";
3045 #clock-cells = <1>;
3049 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
3052 #clock-cells = <1>;
3056 jpgenc-master {
3057 compatible = "mediatek,mt8195-jpgenc";
3058 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3063 #address-cells = <2>;
3064 #size-cells = <2>;
3068 compatible = "mediatek,mt8195-jpgenc-hw";
3076 clock-names = "jpgenc";
3077 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3081 compatible = "mediatek,mt8195-jpgenc-hw";
3089 clock-names = "jpgenc";
3090 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3095 compatible = "mediatek,mt8195-smi-larb";
3097 mediatek,larb-id = <20>;
3102 clock-names = "apb", "smi", "gals";
3103 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3107 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
3110 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3113 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
3117 compatible = "mediatek,mt8195-disp-rdma";
3120 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3123 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
3127 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
3130 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3132 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
3136 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
3139 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3141 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
3145 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
3148 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3150 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
3154 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
3157 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3159 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
3163 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
3166 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3168 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
3172 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3175 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3179 clock-names = "engine", "digital", "hs";
3181 phy-names = "dphy";
3186 compatible = "mediatek,mt8195-disp-dsc";
3189 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3191 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
3195 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3198 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3202 clock-names = "engine", "digital", "hs";
3204 phy-names = "dphy";
3209 compatible = "mediatek,mt8195-disp-merge";
3212 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3214 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3217 dp_intf0: dp-intf@1c015000 {
3218 compatible = "mediatek,mt8195-dp-intf";
3224 clock-names = "engine", "pixel", "pll";
3229 compatible = "mediatek,mt8195-disp-mutex";
3232 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3234 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3238 compatible = "mediatek,mt8195-smi-larb";
3240 mediatek,larb-id = <0>;
3245 clock-names = "apb", "smi", "gals";
3246 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3250 compatible = "mediatek,mt8195-smi-larb";
3252 mediatek,larb-id = <1>;
3257 clock-names = "apb", "smi", "gals";
3258 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3262 compatible = "mediatek,mt8195-vdosys1", "syscon";
3265 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
3266 #clock-cells = <1>;
3267 #reset-cells = <1>;
3271 compatible = "mediatek,mt8195-smi-common-vdo";
3277 clock-names = "apb", "smi", "gals0", "gals1";
3278 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3283 compatible = "mediatek,mt8195-iommu-vdo";
3290 #iommu-cells = <1>;
3292 clock-names = "bclk";
3293 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3297 compatible = "mediatek,mt8195-disp-mutex";
3299 reg-names = "vdo1_mutex";
3301 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3303 clock-names = "vdo1_mutex";
3304 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3308 compatible = "mediatek,mt8195-smi-larb";
3310 mediatek,larb-id = <2>;
3315 clock-names = "apb", "smi", "gals";
3316 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3320 compatible = "mediatek,mt8195-smi-larb";
3322 mediatek,larb-id = <3>;
3327 clock-names = "apb", "smi", "gals";
3328 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3331 vdo1_rdma0: dma-controller@1c104000 {
3332 compatible = "mediatek,mt8195-vdo1-rdma";
3336 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3338 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
3339 #dma-cells = <1>;
3342 vdo1_rdma1: dma-controller@1c105000 {
3343 compatible = "mediatek,mt8195-vdo1-rdma";
3347 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3349 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
3350 #dma-cells = <1>;
3353 vdo1_rdma2: dma-controller@1c106000 {
3354 compatible = "mediatek,mt8195-vdo1-rdma";
3358 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3360 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
3361 #dma-cells = <1>;
3364 vdo1_rdma3: dma-controller@1c107000 {
3365 compatible = "mediatek,mt8195-vdo1-rdma";
3369 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3371 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
3372 #dma-cells = <1>;
3375 vdo1_rdma4: dma-controller@1c108000 {
3376 compatible = "mediatek,mt8195-vdo1-rdma";
3380 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3382 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
3383 #dma-cells = <1>;
3386 vdo1_rdma5: dma-controller@1c109000 {
3387 compatible = "mediatek,mt8195-vdo1-rdma";
3391 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3393 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
3394 #dma-cells = <1>;
3397 vdo1_rdma6: dma-controller@1c10a000 {
3398 compatible = "mediatek,mt8195-vdo1-rdma";
3402 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3404 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
3405 #dma-cells = <1>;
3408 vdo1_rdma7: dma-controller@1c10b000 {
3409 compatible = "mediatek,mt8195-vdo1-rdma";
3413 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3415 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
3416 #dma-cells = <1>;
3419 merge1: vpp-merge@1c10c000 {
3420 compatible = "mediatek,mt8195-disp-merge";
3425 clock-names = "merge","merge_async";
3426 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3427 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
3428 mediatek,merge-mute;
3432 merge2: vpp-merge@1c10d000 {
3433 compatible = "mediatek,mt8195-disp-merge";
3438 clock-names = "merge","merge_async";
3439 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3440 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
3441 mediatek,merge-mute;
3445 merge3: vpp-merge@1c10e000 {
3446 compatible = "mediatek,mt8195-disp-merge";
3451 clock-names = "merge","merge_async";
3452 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3453 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
3454 mediatek,merge-mute;
3458 merge4: vpp-merge@1c10f000 {
3459 compatible = "mediatek,mt8195-disp-merge";
3464 clock-names = "merge","merge_async";
3465 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3466 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3467 mediatek,merge-mute;
3471 merge5: vpp-merge@1c110000 {
3472 compatible = "mediatek,mt8195-disp-merge";
3477 clock-names = "merge","merge_async";
3478 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3479 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3480 mediatek,merge-fifo-en;
3484 dp_intf1: dp-intf@1c113000 {
3485 compatible = "mediatek,mt8195-dp-intf";
3488 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3492 clock-names = "engine", "pixel", "pll";
3496 ethdr0: hdr-engine@1c114000 {
3497 compatible = "mediatek,mt8195-disp-ethdr";
3505 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3507 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3527 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3531 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3540 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
3544 edp_tx: edp-tx@1c500000 {
3545 compatible = "mediatek,mt8195-edp-tx";
3547 nvmem-cells = <&dp_calibration>;
3548 nvmem-cell-names = "dp_calibration_data";
3549 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3551 max-linkrate-mhz = <8100>;
3555 dp_tx: dp-tx@1c600000 {
3556 compatible = "mediatek,mt8195-dp-tx";
3558 nvmem-cells = <&dp_calibration>;
3559 nvmem-cell-names = "dp_calibration_data";
3560 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3562 max-linkrate-mhz = <8100>;
3567 thermal_zones: thermal-zones {
3568 cpu0-thermal {
3569 polling-delay = <1000>;
3570 polling-delay-passive = <250>;
3571 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3574 cpu0_alert: trip-alert {
3580 cpu0_crit: trip-crit {
3587 cooling-maps {
3590 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3598 cpu1-thermal {
3599 polling-delay = <1000>;
3600 polling-delay-passive = <250>;
3601 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3604 cpu1_alert: trip-alert {
3610 cpu1_crit: trip-crit {
3617 cooling-maps {
3620 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3628 cpu2-thermal {
3629 polling-delay = <1000>;
3630 polling-delay-passive = <250>;
3631 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3634 cpu2_alert: trip-alert {
3640 cpu2_crit: trip-crit {
3647 cooling-maps {
3650 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3658 cpu3-thermal {
3659 polling-delay = <1000>;
3660 polling-delay-passive = <250>;
3661 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3664 cpu3_alert: trip-alert {
3670 cpu3_crit: trip-crit {
3677 cooling-maps {
3680 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3688 cpu4-thermal {
3689 polling-delay = <1000>;
3690 polling-delay-passive = <250>;
3691 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3694 cpu4_alert: trip-alert {
3700 cpu4_crit: trip-crit {
3707 cooling-maps {
3710 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3718 cpu5-thermal {
3719 polling-delay = <1000>;
3720 polling-delay-passive = <250>;
3721 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3724 cpu5_alert: trip-alert {
3730 cpu5_crit: trip-crit {
3737 cooling-maps {
3740 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3748 cpu6-thermal {
3749 polling-delay = <1000>;
3750 polling-delay-passive = <250>;
3751 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3754 cpu6_alert: trip-alert {
3760 cpu6_crit: trip-crit {
3767 cooling-maps {
3770 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3778 cpu7-thermal {
3779 polling-delay = <1000>;
3780 polling-delay-passive = <250>;
3781 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3784 cpu7_alert: trip-alert {
3790 cpu7_crit: trip-crit {
3797 cooling-maps {
3800 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3808 vpu0-thermal {
3809 polling-delay = <1000>;
3810 polling-delay-passive = <250>;
3811 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
3814 vpu0_alert: trip-alert {
3820 vpu0_crit: trip-crit {
3828 vpu1-thermal {
3829 polling-delay = <1000>;
3830 polling-delay-passive = <250>;
3831 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
3834 vpu1_alert: trip-alert {
3840 vpu1_crit: trip-crit {
3848 gpu0-thermal {
3849 polling-delay = <1000>;
3850 polling-delay-passive = <250>;
3851 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
3854 gpu0_alert: trip-alert {
3860 gpu0_crit: trip-crit {
3868 gpu1-thermal {
3869 polling-delay = <1000>;
3870 polling-delay-passive = <250>;
3871 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
3874 gpu1_alert: trip-alert {
3880 gpu1_crit: trip-crit {
3888 vdec-thermal {
3889 polling-delay = <1000>;
3890 polling-delay-passive = <250>;
3891 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
3894 vdec_alert: trip-alert {
3900 vdec_crit: trip-crit {
3908 img-thermal {
3909 polling-delay = <1000>;
3910 polling-delay-passive = <250>;
3911 thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
3914 img_alert: trip-alert {
3920 img_crit: trip-crit {
3928 infra-thermal {
3929 polling-delay = <1000>;
3930 polling-delay-passive = <250>;
3931 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
3934 infra_alert: trip-alert {
3940 infra_crit: trip-crit {
3948 cam0-thermal {
3949 polling-delay = <1000>;
3950 polling-delay-passive = <250>;
3951 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
3954 cam0_alert: trip-alert {
3960 cam0_crit: trip-crit {
3968 cam1-thermal {
3969 polling-delay = <1000>;
3970 polling-delay-passive = <250>;
3971 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
3974 cam1_alert: trip-alert {
3980 cam1_crit: trip-crit {