Lines Matching +full:1 +full:c114000
50 #address-cells = <1>;
134 performance-domains = <&performance 1>;
153 performance-domains = <&performance 1>;
172 performance-domains = <&performance 1>;
191 performance-domains = <&performance 1>;
335 clock-mult = <1>;
356 #performance-domain-cells = <1>;
465 #redistributor-regions = <1>;
477 ppi_cluster1: interrupt-partition-1 {
486 #clock-cells = <1>;
492 #clock-cells = <1>;
493 #reset-cells = <1>;
499 #clock-cells = <1>;
530 #address-cells = <1>;
532 #power-domain-cells = <1>;
537 #address-cells = <1>;
539 #power-domain-cells = <1>;
547 #address-cells = <1>;
549 #power-domain-cells = <1>;
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
616 #address-cells = <1>;
618 #power-domain-cells = <1>;
645 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
649 #address-cells = <1>;
651 #power-domain-cells = <1>;
659 "vppsys1-1";
670 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
707 "vdosys1-1", "vdosys1-2";
709 #address-cells = <1>;
711 #power-domain-cells = <1>;
737 clock-names = "img-0", "img-1";
739 #address-cells = <1>;
741 #power-domain-cells = <1>;
753 clock-names = "ipe", "ipe-0", "ipe-1";
766 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
769 #address-cells = <1>;
771 #power-domain-cells = <1>;
833 #address-cells = <1>;
836 #power-domain-cells = <1>;
857 #reset-cells = <1>;
863 #clock-cells = <1>;
909 #iommu-cells = <1>;
941 #clock-cells = <1>;
1096 #io-channel-cells = <1>;
1103 #clock-cells = <1>;
1109 #address-cells = <1>;
1127 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1128 #thermal-sensor-cells = <1>;
1169 #address-cells = <1>;
1183 #address-cells = <1>;
1197 #address-cells = <1>;
1211 #address-cells = <1>;
1225 #address-cells = <1>;
1293 #address-cells = <1>;
1425 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1426 #thermal-sensor-cells = <1>;
1538 #interrupt-cells = <1>;
1540 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1541 <0 0 0 2 &pcie_intc0 1>,
1549 #interrupt-cells = <1>;
1590 #interrupt-cells = <1>;
1592 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1593 <0 0 0 2 &pcie_intc1 1>,
1601 #interrupt-cells = <1>;
1614 #address-cells = <1>;
1622 #address-cells = <1>;
1623 #size-cells = <1>;
1624 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1636 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1648 u2_intr_p0: usb2-intr-p0@188,1 {
1656 u2_intr_p2: usb2-intr-p2@189,1 {
1664 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1672 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1680 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1692 dp_calibration: dp-data@1ac {
1695 lvts_efuse_data1: lvts1-calib@1bc {
1698 lvts_efuse_data2: lvts2-calib@1d0 {
1708 #address-cells = <1>;
1709 #size-cells = <1>;
1717 #phy-cells = <1>;
1723 #address-cells = <1>;
1724 #size-cells = <1>;
1732 #phy-cells = <1>;
1762 clock-div = <1>;
1766 #address-cells = <1>;
1777 clock-div = <1>;
1781 #address-cells = <1>;
1792 clock-div = <1>;
1796 #address-cells = <1>;
1804 #clock-cells = <1>;
1813 clock-div = <1>;
1817 #address-cells = <1>;
1828 clock-div = <1>;
1832 #address-cells = <1>;
1843 clock-div = <1>;
1847 #address-cells = <1>;
1858 clock-div = <1>;
1862 #address-cells = <1>;
1873 clock-div = <1>;
1877 #address-cells = <1>;
1885 #clock-cells = <1>;
1890 #address-cells = <1>;
1891 #size-cells = <1>;
1901 #phy-cells = <1>;
1913 #phy-cells = <1>;
1919 #address-cells = <1>;
1920 #size-cells = <1>;
1929 #phy-cells = <1>;
1941 #phy-cells = <1>;
1994 #clock-cells = <1>;
2000 #clock-cells = <1>;
2017 #dma-cells = <1>;
2109 #dma-cells = <1>;
2175 #iommu-cells = <1>;
2182 #clock-cells = <1>;
2188 #clock-cells = <1>;
2194 #clock-cells = <1>;
2223 #clock-cells = <1>;
2285 #dma-cells = <1>;
2297 #dma-cells = <1>;
2309 #dma-cells = <1>;
2515 #dma-cells = <1>;
2527 #dma-cells = <1>;
2539 #dma-cells = <1>;
2545 #clock-cells = <1>;
2585 #clock-cells = <1>;
2602 #clock-cells = <1>;
2608 #clock-cells = <1>;
2625 #clock-cells = <1>;
2642 #clock-cells = <1>;
2737 #clock-cells = <1>;
2743 #clock-cells = <1>;
2749 #clock-cells = <1>;
2755 #clock-cells = <1>;
2761 #clock-cells = <1>;
2791 #clock-cells = <1>;
2900 #clock-cells = <1>;
2917 #clock-cells = <1>;
2934 #clock-cells = <1>;
2940 #clock-cells = <1>;
2943 vencsys: clock-controller@1a000000 {
2946 #clock-cells = <1>;
2949 larb19: larb@1a010000 {
2960 venc: video-codec@1a020000 {
2996 jpgdec@1a040000 {
3011 jpgdec@1a050000 {
3026 jpgdec@1b040000 {
3042 vencsys_core1: clock-controller@1b000000 {
3045 #clock-cells = <1>;
3048 vdosys0: syscon@1c01a000 {
3052 #clock-cells = <1>;
3067 jpgenc@1a030000 {
3080 jpgenc@1b030000 {
3094 larb20: larb@1b010000 {
3106 ovl0: ovl@1c000000 {
3116 rdma0: rdma@1c002000 {
3126 color0: color@1c003000 {
3135 ccorr0: ccorr@1c004000 {
3144 aal0: aal@1c005000 {
3153 gamma0: gamma@1c006000 {
3162 dither0: dither@1c007000 {
3171 dsi0: dsi@1c008000 {
3185 dsc0: dsc@1c009000 {
3194 dsi1: dsi@1c012000 {
3208 merge0: merge@1c014000 {
3217 dp_intf0: dp-intf@1c015000 {
3228 mutex: mutex@1c016000 {
3237 larb0: larb@1c018000 {
3249 larb1: larb@1c019000 {
3252 mediatek,larb-id = <1>;
3261 vdosys1: syscon@1c100000 {
3264 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
3266 #clock-cells = <1>;
3267 #reset-cells = <1>;
3270 smi_common_vdo: smi@1c01b000 {
3282 iommu_vdo: iommu@1c01f000 {
3290 #iommu-cells = <1>;
3296 mutex1: mutex@1c101000 {
3307 larb2: larb@1c102000 {
3319 larb3: larb@1c103000 {
3331 vdo1_rdma0: dma-controller@1c104000 {
3339 #dma-cells = <1>;
3342 vdo1_rdma1: dma-controller@1c105000 {
3350 #dma-cells = <1>;
3353 vdo1_rdma2: dma-controller@1c106000 {
3361 #dma-cells = <1>;
3364 vdo1_rdma3: dma-controller@1c107000 {
3372 #dma-cells = <1>;
3375 vdo1_rdma4: dma-controller@1c108000 {
3383 #dma-cells = <1>;
3386 vdo1_rdma5: dma-controller@1c109000 {
3394 #dma-cells = <1>;
3397 vdo1_rdma6: dma-controller@1c10a000 {
3405 #dma-cells = <1>;
3408 vdo1_rdma7: dma-controller@1c10b000 {
3416 #dma-cells = <1>;
3419 merge1: vpp-merge@1c10c000 {
3432 merge2: vpp-merge@1c10d000 {
3445 merge3: vpp-merge@1c10e000 {
3458 merge4: vpp-merge@1c10f000 {
3471 merge5: vpp-merge@1c110000 {
3484 dp_intf1: dp-intf@1c113000 {
3496 ethdr0: hdr-engine@1c114000 {
3544 edp_tx: edp-tx@1c500000 {
3555 dp_tx: dp-tx@1c600000 {