Lines Matching +full:mtk +full:- +full:gce
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
16 #include <dt-bindings/reset/mt8192-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
28 ovl-2l0 = &ovl_2l0;
29 ovl-2l2 = &ovl_2l2;
34 clk13m: fixed-factor-clock-13m {
35 compatible = "fixed-factor-clock";
36 #clock-cells = <0>;
38 clock-div = <2>;
39 clock-mult = <1>;
40 clock-output-names = "clk13m";
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <26000000>;
47 clock-output-names = "clk26m";
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <32768>;
54 clock-output-names = "clk32k";
58 #address-cells = <1>;
59 #size-cells = <0>;
63 compatible = "arm,cortex-a55";
65 enable-method = "psci";
66 clock-frequency = <1701000000>;
67 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
68 i-cache-size = <32768>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <128>;
71 d-cache-size = <32768>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
74 next-level-cache = <&l2_0>;
75 performance-domains = <&performance 0>;
76 capacity-dmips-mhz = <427>;
77 #cooling-cells = <2>;
82 compatible = "arm,cortex-a55";
84 enable-method = "psci";
85 clock-frequency = <1701000000>;
86 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
87 i-cache-size = <32768>;
88 i-cache-line-size = <64>;
89 i-cache-sets = <128>;
90 d-cache-size = <32768>;
91 d-cache-line-size = <64>;
92 d-cache-sets = <128>;
93 next-level-cache = <&l2_0>;
94 performance-domains = <&performance 0>;
95 capacity-dmips-mhz = <427>;
96 #cooling-cells = <2>;
101 compatible = "arm,cortex-a55";
103 enable-method = "psci";
104 clock-frequency = <1701000000>;
105 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
106 i-cache-size = <32768>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <128>;
109 d-cache-size = <32768>;
110 d-cache-line-size = <64>;
111 d-cache-sets = <128>;
112 next-level-cache = <&l2_0>;
113 performance-domains = <&performance 0>;
114 capacity-dmips-mhz = <427>;
115 #cooling-cells = <2>;
120 compatible = "arm,cortex-a55";
122 enable-method = "psci";
123 clock-frequency = <1701000000>;
124 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
125 i-cache-size = <32768>;
126 i-cache-line-size = <64>;
127 i-cache-sets = <128>;
128 d-cache-size = <32768>;
129 d-cache-line-size = <64>;
130 d-cache-sets = <128>;
131 next-level-cache = <&l2_0>;
132 performance-domains = <&performance 0>;
133 capacity-dmips-mhz = <427>;
134 #cooling-cells = <2>;
139 compatible = "arm,cortex-a76";
141 enable-method = "psci";
142 clock-frequency = <2171000000>;
143 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
144 i-cache-size = <65536>;
145 i-cache-line-size = <64>;
146 i-cache-sets = <256>;
147 d-cache-size = <65536>;
148 d-cache-line-size = <64>;
149 d-cache-sets = <256>;
150 next-level-cache = <&l2_1>;
151 performance-domains = <&performance 1>;
152 capacity-dmips-mhz = <1024>;
153 #cooling-cells = <2>;
158 compatible = "arm,cortex-a76";
160 enable-method = "psci";
161 clock-frequency = <2171000000>;
162 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
163 i-cache-size = <65536>;
164 i-cache-line-size = <64>;
165 i-cache-sets = <256>;
166 d-cache-size = <65536>;
167 d-cache-line-size = <64>;
168 d-cache-sets = <256>;
169 next-level-cache = <&l2_1>;
170 performance-domains = <&performance 1>;
171 capacity-dmips-mhz = <1024>;
172 #cooling-cells = <2>;
177 compatible = "arm,cortex-a76";
179 enable-method = "psci";
180 clock-frequency = <2171000000>;
181 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
182 i-cache-size = <65536>;
183 i-cache-line-size = <64>;
184 i-cache-sets = <256>;
185 d-cache-size = <65536>;
186 d-cache-line-size = <64>;
187 d-cache-sets = <256>;
188 next-level-cache = <&l2_1>;
189 performance-domains = <&performance 1>;
190 capacity-dmips-mhz = <1024>;
191 #cooling-cells = <2>;
196 compatible = "arm,cortex-a76";
198 enable-method = "psci";
199 clock-frequency = <2171000000>;
200 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
201 i-cache-size = <65536>;
202 i-cache-line-size = <64>;
203 i-cache-sets = <256>;
204 d-cache-size = <65536>;
205 d-cache-line-size = <64>;
206 d-cache-sets = <256>;
207 next-level-cache = <&l2_1>;
208 performance-domains = <&performance 1>;
209 capacity-dmips-mhz = <1024>;
210 #cooling-cells = <2>;
213 cpu-map {
242 l2_0: l2-cache0 {
244 cache-level = <2>;
245 cache-size = <131072>;
246 cache-line-size = <64>;
247 cache-sets = <512>;
248 next-level-cache = <&l3_0>;
249 cache-unified;
252 l2_1: l2-cache1 {
254 cache-level = <2>;
255 cache-size = <262144>;
256 cache-line-size = <64>;
257 cache-sets = <512>;
258 next-level-cache = <&l3_0>;
259 cache-unified;
262 l3_0: l3-cache {
264 cache-level = <3>;
265 cache-size = <2097152>;
266 cache-line-size = <64>;
267 cache-sets = <2048>;
268 cache-unified;
271 idle-states {
272 entry-method = "psci";
273 cpu_ret_l: cpu-retention-l {
274 compatible = "arm,idle-state";
275 arm,psci-suspend-param = <0x00010001>;
276 local-timer-stop;
277 entry-latency-us = <55>;
278 exit-latency-us = <140>;
279 min-residency-us = <780>;
281 cpu_ret_b: cpu-retention-b {
282 compatible = "arm,idle-state";
283 arm,psci-suspend-param = <0x00010001>;
284 local-timer-stop;
285 entry-latency-us = <35>;
286 exit-latency-us = <145>;
287 min-residency-us = <720>;
289 cpu_off_l: cpu-off-l {
290 compatible = "arm,idle-state";
291 arm,psci-suspend-param = <0x01010002>;
292 local-timer-stop;
293 entry-latency-us = <60>;
294 exit-latency-us = <155>;
295 min-residency-us = <860>;
297 cpu_off_b: cpu-off-b {
298 compatible = "arm,idle-state";
299 arm,psci-suspend-param = <0x01010002>;
300 local-timer-stop;
301 entry-latency-us = <40>;
302 exit-latency-us = <155>;
303 min-residency-us = <780>;
308 pmu-a55 {
309 compatible = "arm,cortex-a55-pmu";
310 interrupt-parent = <&gic>;
314 pmu-a76 {
315 compatible = "arm,cortex-a76-pmu";
316 interrupt-parent = <&gic>;
321 compatible = "arm,psci-1.0";
326 compatible = "arm,armv8-timer";
327 interrupt-parent = <&gic>;
332 clock-frequency = <13000000>;
335 gpu_opp_table: opp-table-0 {
336 compatible = "operating-points-v2";
337 opp-shared;
339 opp-358000000 {
340 opp-hz = /bits/ 64 <358000000>;
341 opp-microvolt = <606250>;
344 opp-399000000 {
345 opp-hz = /bits/ 64 <399000000>;
346 opp-microvolt = <618750>;
349 opp-440000000 {
350 opp-hz = /bits/ 64 <440000000>;
351 opp-microvolt = <631250>;
354 opp-482000000 {
355 opp-hz = /bits/ 64 <482000000>;
356 opp-microvolt = <643750>;
359 opp-523000000 {
360 opp-hz = /bits/ 64 <523000000>;
361 opp-microvolt = <656250>;
364 opp-564000000 {
365 opp-hz = /bits/ 64 <564000000>;
366 opp-microvolt = <668750>;
369 opp-605000000 {
370 opp-hz = /bits/ 64 <605000000>;
371 opp-microvolt = <681250>;
374 opp-647000000 {
375 opp-hz = /bits/ 64 <647000000>;
376 opp-microvolt = <693750>;
379 opp-688000000 {
380 opp-hz = /bits/ 64 <688000000>;
381 opp-microvolt = <706250>;
384 opp-724000000 {
385 opp-hz = /bits/ 64 <724000000>;
386 opp-microvolt = <725000>;
389 opp-748000000 {
390 opp-hz = /bits/ 64 <748000000>;
391 opp-microvolt = <737500>;
394 opp-772000000 {
395 opp-hz = /bits/ 64 <772000000>;
396 opp-microvolt = <750000>;
399 opp-795000000 {
400 opp-hz = /bits/ 64 <795000000>;
401 opp-microvolt = <762500>;
404 opp-819000000 {
405 opp-hz = /bits/ 64 <819000000>;
406 opp-microvolt = <775000>;
409 opp-843000000 {
410 opp-hz = /bits/ 64 <843000000>;
411 opp-microvolt = <787500>;
414 opp-866000000 {
415 opp-hz = /bits/ 64 <866000000>;
416 opp-microvolt = <800000>;
421 #address-cells = <2>;
422 #size-cells = <2>;
423 compatible = "simple-bus";
424 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
427 performance: performance-controller@11bc10 {
428 compatible = "mediatek,cpufreq-hw";
430 #performance-domain-cells = <1>;
433 gic: interrupt-controller@c000000 {
434 compatible = "arm,gic-v3";
435 #interrupt-cells = <4>;
436 #redistributor-regions = <1>;
437 interrupt-parent = <&gic>;
438 interrupt-controller;
443 ppi-partitions {
444 ppi_cluster0: interrupt-partition-0 {
447 ppi_cluster1: interrupt-partition-1 {
454 compatible = "mediatek,mt8192-topckgen", "syscon";
456 #clock-cells = <1>;
460 compatible = "mediatek,mt8192-infracfg", "syscon";
462 #clock-cells = <1>;
463 #reset-cells = <1>;
467 compatible = "mediatek,mt8192-pericfg", "syscon";
469 #clock-cells = <1>;
473 compatible = "mediatek,mt8192-pinctrl";
485 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
489 gpio-controller;
490 #gpio-cells = <2>;
491 gpio-ranges = <&pio 0 0 220>;
492 interrupt-controller;
494 #interrupt-cells = <2>;
498 compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd";
502 spm: power-controller {
503 compatible = "mediatek,mt8192-power-controller";
504 #address-cells = <1>;
505 #size-cells = <0>;
506 #power-domain-cells = <1>;
509 power-domain@MT8192_POWER_DOMAIN_AUDIO {
514 clock-names = "audio", "audio1", "audio2";
516 #power-domain-cells = <0>;
519 power-domain@MT8192_POWER_DOMAIN_CONN {
522 clock-names = "conn";
524 #power-domain-cells = <0>;
527 mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 {
531 clock-names = "mfg", "alt";
532 #address-cells = <1>;
533 #size-cells = <0>;
534 #power-domain-cells = <1>;
536 mfg1: power-domain@MT8192_POWER_DOMAIN_MFG1 {
539 #address-cells = <1>;
540 #size-cells = <0>;
541 #power-domain-cells = <1>;
543 power-domain@MT8192_POWER_DOMAIN_MFG2 {
545 #power-domain-cells = <0>;
548 power-domain@MT8192_POWER_DOMAIN_MFG3 {
550 #power-domain-cells = <0>;
553 power-domain@MT8192_POWER_DOMAIN_MFG4 {
555 #power-domain-cells = <0>;
558 power-domain@MT8192_POWER_DOMAIN_MFG5 {
560 #power-domain-cells = <0>;
563 power-domain@MT8192_POWER_DOMAIN_MFG6 {
565 #power-domain-cells = <0>;
570 power-domain@MT8192_POWER_DOMAIN_DISP {
577 clock-names = "disp", "disp-0", "disp-1", "disp-2",
578 "disp-3";
580 #address-cells = <1>;
581 #size-cells = <0>;
582 #power-domain-cells = <1>;
584 power-domain@MT8192_POWER_DOMAIN_IPE {
591 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
592 "ipe-3";
594 #power-domain-cells = <0>;
597 power-domain@MT8192_POWER_DOMAIN_ISP {
602 clock-names = "isp", "isp-0", "isp-1";
604 #power-domain-cells = <0>;
607 power-domain@MT8192_POWER_DOMAIN_ISP2 {
612 clock-names = "isp2", "isp2-0", "isp2-1";
614 #power-domain-cells = <0>;
617 power-domain@MT8192_POWER_DOMAIN_MDP {
621 clock-names = "mdp", "mdp-0";
623 #power-domain-cells = <0>;
626 power-domain@MT8192_POWER_DOMAIN_VENC {
630 clock-names = "venc", "venc-0";
632 #power-domain-cells = <0>;
635 power-domain@MT8192_POWER_DOMAIN_VDEC {
641 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
643 #address-cells = <1>;
644 #size-cells = <0>;
645 #power-domain-cells = <1>;
647 power-domain@MT8192_POWER_DOMAIN_VDEC2 {
652 clock-names = "vdec2-0", "vdec2-1",
653 "vdec2-2";
654 #power-domain-cells = <0>;
658 power-domain@MT8192_POWER_DOMAIN_CAM {
665 clock-names = "cam", "cam-0", "cam-1", "cam-2",
666 "cam-3";
668 #address-cells = <1>;
669 #size-cells = <0>;
670 #power-domain-cells = <1>;
672 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {
675 clock-names = "cam_rawa-0";
676 #power-domain-cells = <0>;
679 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {
682 clock-names = "cam_rawb-0";
683 #power-domain-cells = <0>;
686 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {
689 clock-names = "cam_rawc-0";
690 #power-domain-cells = <0>;
698 compatible = "mediatek,mt8192-wdt";
700 #reset-cells = <1>;
704 compatible = "mediatek,mt8192-apmixedsys", "syscon";
706 #clock-cells = <1>;
710 compatible = "mediatek,mt8192-timer",
711 "mediatek,mt6765-timer";
718 compatible = "mediatek,mt6873-pwrap";
720 reg-names = "pwrap";
724 clock-names = "spi", "wrap";
725 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
726 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
730 compatible = "mediatek,mt6873-spmi";
733 reg-names = "pmif", "spmimst";
737 clock-names = "pmif_sys_ck",
740 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
741 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
744 gce: mailbox@10228000 {
745 compatible = "mediatek,mt8192-gce";
748 #mbox-cells = <2>;
750 clock-names = "gce";
753 scp_adsp: clock-controller@10720000 {
754 compatible = "mediatek,mt8192-scp_adsp";
756 #clock-cells = <1>;
762 compatible = "mediatek,mt8192-uart",
763 "mediatek,mt6577-uart";
767 clock-names = "baud", "bus";
772 compatible = "mediatek,mt8192-uart",
773 "mediatek,mt6577-uart";
777 clock-names = "baud", "bus";
781 imp_iic_wrap_c: clock-controller@11007000 {
782 compatible = "mediatek,mt8192-imp_iic_wrap_c";
784 #clock-cells = <1>;
788 compatible = "mediatek,mt8192-spi",
789 "mediatek,mt6765-spi";
790 #address-cells = <1>;
791 #size-cells = <0>;
797 clock-names = "parent-clk", "sel-clk", "spi-clk";
801 lvts_ap: thermal-sensor@1100b000 {
802 compatible = "mediatek,mt8192-lvts-ap";
807 nvmem-cells = <&lvts_e_data1>;
808 nvmem-cell-names = "lvts-calib-data-1";
809 #thermal-sensor-cells = <1>;
813 compatible = "mediatek,mt8192-svs";
817 clock-names = "main";
818 nvmem-cells = <&svs_calibration>, <&lvts_e_data1>;
819 nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
821 reset-names = "svs_rst";
825 compatible = "mediatek,mt8183-disp-pwm";
828 #pwm-cells = <2>;
831 clock-names = "main", "mm";
836 compatible = "mediatek,mt8192-spi",
837 "mediatek,mt6765-spi";
838 #address-cells = <1>;
839 #size-cells = <0>;
845 clock-names = "parent-clk", "sel-clk", "spi-clk";
850 compatible = "mediatek,mt8192-spi",
851 "mediatek,mt6765-spi";
852 #address-cells = <1>;
853 #size-cells = <0>;
859 clock-names = "parent-clk", "sel-clk", "spi-clk";
864 compatible = "mediatek,mt8192-spi",
865 "mediatek,mt6765-spi";
866 #address-cells = <1>;
867 #size-cells = <0>;
873 clock-names = "parent-clk", "sel-clk", "spi-clk";
878 compatible = "mediatek,mt8192-spi",
879 "mediatek,mt6765-spi";
880 #address-cells = <1>;
881 #size-cells = <0>;
887 clock-names = "parent-clk", "sel-clk", "spi-clk";
892 compatible = "mediatek,mt8192-spi",
893 "mediatek,mt6765-spi";
894 #address-cells = <1>;
895 #size-cells = <0>;
901 clock-names = "parent-clk", "sel-clk", "spi-clk";
906 compatible = "mediatek,mt8192-spi",
907 "mediatek,mt6765-spi";
908 #address-cells = <1>;
909 #size-cells = <0>;
915 clock-names = "parent-clk", "sel-clk", "spi-clk";
920 compatible = "mediatek,mt8192-spi",
921 "mediatek,mt6765-spi";
922 #address-cells = <1>;
923 #size-cells = <0>;
929 clock-names = "parent-clk", "sel-clk", "spi-clk";
934 compatible = "mediatek,mt8192-scp";
938 reg-names = "sram", "cfg", "l1tcm";
941 clock-names = "main";
946 compatible = "mediatek,mt8192-xhci",
947 "mediatek,mtk-xhci";
950 reg-names = "mac", "ippc";
951 interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
952 interrupt-names = "host";
955 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
957 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
964 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
966 wakeup-source;
967 mediatek,syscon-wakeup = <&pericfg 0x420 102>;
972 compatible = "mediatek,mt8192-audsys", "syscon";
974 #clock-cells = <1>;
976 afe: mt8192-afe-pcm {
977 compatible = "mediatek,mt8192-audio";
980 reset-names = "audiosys";
984 power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
1041 clock-names = "aud_afe_clk",
1101 compatible = "mediatek,mt8192-pcie";
1104 reg-names = "pcie-mac";
1105 #address-cells = <3>;
1106 #size-cells = <2>;
1113 clock-names = "pl_250m", "tl_26m", "tl_96m",
1115 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
1116 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
1118 bus-range = <0x00 0xff>;
1121 #interrupt-cells = <1>;
1122 interrupt-map-mask = <0 0 0 7>;
1123 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1128 pcie_intc0: interrupt-controller {
1129 interrupt-controller;
1130 #address-cells = <0>;
1131 #interrupt-cells = <1>;
1136 compatible = "mediatek,mt8192-nor";
1142 clock-names = "spi", "sf", "axi";
1143 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
1144 assigned-clock-parents = <&clk26m>;
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1150 lvts_mcu: thermal-sensor@11278000 {
1151 compatible = "mediatek,mt8192-lvts-mcu";
1156 nvmem-cells = <&lvts_e_data1>;
1157 nvmem-cell-names = "lvts-calib-data-1";
1158 #thermal-sensor-cells = <1>;
1162 compatible = "mediatek,mt8192-efuse", "mediatek,efuse";
1164 #address-cells = <1>;
1165 #size-cells = <1>;
1177 compatible = "mediatek,mt8192-i2c";
1183 clock-names = "main", "dma";
1184 clock-div = <1>;
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1190 imp_iic_wrap_e: clock-controller@11cb1000 {
1191 compatible = "mediatek,mt8192-imp_iic_wrap_e";
1193 #clock-cells = <1>;
1197 compatible = "mediatek,mt8192-i2c";
1203 clock-names = "main", "dma";
1204 clock-div = <1>;
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1211 compatible = "mediatek,mt8192-i2c";
1217 clock-names = "main", "dma";
1218 clock-div = <1>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1225 compatible = "mediatek,mt8192-i2c";
1231 clock-names = "main", "dma";
1232 clock-div = <1>;
1233 #address-cells = <1>;
1234 #size-cells = <0>;
1238 imp_iic_wrap_s: clock-controller@11d03000 {
1239 compatible = "mediatek,mt8192-imp_iic_wrap_s";
1241 #clock-cells = <1>;
1245 compatible = "mediatek,mt8192-i2c";
1251 clock-names = "main", "dma";
1252 clock-div = <1>;
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1259 compatible = "mediatek,mt8192-i2c";
1265 clock-names = "main", "dma";
1266 clock-div = <1>;
1267 #address-cells = <1>;
1268 #size-cells = <0>;
1273 compatible = "mediatek,mt8192-i2c";
1279 clock-names = "main", "dma";
1280 clock-div = <1>;
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1286 imp_iic_wrap_ws: clock-controller@11d23000 {
1287 compatible = "mediatek,mt8192-imp_iic_wrap_ws";
1289 #clock-cells = <1>;
1293 compatible = "mediatek,mt8192-i2c";
1299 clock-names = "main", "dma";
1300 clock-div = <1>;
1301 #address-cells = <1>;
1302 #size-cells = <0>;
1306 imp_iic_wrap_w: clock-controller@11e01000 {
1307 compatible = "mediatek,mt8192-imp_iic_wrap_w";
1309 #clock-cells = <1>;
1312 u3phy0: t-phy@11e40000 {
1313 compatible = "mediatek,mt8192-tphy",
1314 "mediatek,generic-tphy-v2";
1315 #address-cells = <1>;
1316 #size-cells = <1>;
1319 u2port0: usb-phy@0 {
1322 clock-names = "ref";
1323 #phy-cells = <1>;
1326 u3port0: usb-phy@700 {
1329 clock-names = "ref";
1330 #phy-cells = <1>;
1334 mipi_tx0: dsi-phy@11e50000 {
1335 compatible = "mediatek,mt8183-mipi-tx";
1338 #clock-cells = <0>;
1339 #phy-cells = <0>;
1340 clock-output-names = "mipi_tx0_pll";
1345 compatible = "mediatek,mt8192-i2c";
1351 clock-names = "main", "dma";
1352 clock-div = <1>;
1353 #address-cells = <1>;
1354 #size-cells = <0>;
1359 compatible = "mediatek,mt8192-i2c";
1365 clock-names = "main", "dma";
1366 clock-div = <1>;
1367 #address-cells = <1>;
1368 #size-cells = <0>;
1372 imp_iic_wrap_n: clock-controller@11f02000 {
1373 compatible = "mediatek,mt8192-imp_iic_wrap_n";
1375 #clock-cells = <1>;
1378 msdc_top: clock-controller@11f10000 {
1379 compatible = "mediatek,mt8192-msdc_top";
1381 #clock-cells = <1>;
1385 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1395 clock-names = "source", "hclk", "source_cg", "sys_cg",
1401 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1411 clock-names = "source", "hclk", "source_cg", "sys_cg",
1417 compatible = "mediatek,mt8192-mali", "arm,mali-valhall-jm";
1422 interrupt-names = "job", "mmu", "gpu";
1426 power-domains = <&spm MT8192_POWER_DOMAIN_MFG2>,
1431 power-domain-names = "core0", "core1", "core2", "core3", "core4";
1433 operating-points-v2 = <&gpu_opp_table>;
1438 mfgcfg: clock-controller@13fbf000 {
1439 compatible = "mediatek,mt8192-mfgcfg";
1441 #clock-cells = <1>;
1445 compatible = "mediatek,mt8192-mmsys", "syscon";
1447 #clock-cells = <1>;
1448 #reset-cells = <1>;
1449 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1450 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1451 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1455 compatible = "mediatek,mt8192-disp-mutex";
1459 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1461 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1465 compatible = "mediatek,mt8192-smi-common";
1471 clock-names = "apb", "smi", "gals0", "gals1";
1472 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1476 compatible = "mediatek,mt8192-smi-larb";
1478 mediatek,larb-id = <0>;
1481 clock-names = "apb", "smi";
1482 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1486 compatible = "mediatek,mt8192-smi-larb";
1488 mediatek,larb-id = <1>;
1491 clock-names = "apb", "smi";
1492 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1496 compatible = "mediatek,mt8192-disp-ovl";
1502 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1503 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1507 compatible = "mediatek,mt8192-disp-ovl-2l";
1510 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1514 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1518 compatible = "mediatek,mt8192-disp-rdma",
1519 "mediatek,mt8183-disp-rdma";
1524 mediatek,rdma-fifo-size = <5120>;
1525 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1526 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1530 compatible = "mediatek,mt8192-disp-color",
1531 "mediatek,mt8173-disp-color";
1534 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1536 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1540 compatible = "mediatek,mt8192-disp-ccorr";
1543 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1545 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1549 compatible = "mediatek,mt8192-disp-aal",
1550 "mediatek,mt8183-disp-aal";
1553 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1555 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1559 compatible = "mediatek,mt8192-disp-gamma",
1560 "mediatek,mt8183-disp-gamma";
1563 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1565 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1569 compatible = "mediatek,mt8192-disp-postmask";
1572 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1574 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1578 compatible = "mediatek,mt8192-disp-dither",
1579 "mediatek,mt8183-disp-dither";
1582 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1584 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1588 compatible = "mediatek,mt8183-dsi";
1594 clock-names = "engine", "digital", "hs";
1596 phy-names = "dphy";
1597 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1607 compatible = "mediatek,mt8192-disp-ovl-2l";
1610 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1614 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1618 compatible = "mediatek,mt8192-disp-rdma",
1619 "mediatek,mt8183-disp-rdma";
1622 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1625 mediatek,rdma-fifo-size = <2048>;
1626 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1630 compatible = "mediatek,mt8192-dpi";
1636 clock-names = "pixel", "engine", "pll";
1641 compatible = "mediatek,mt8192-m4u";
1650 clock-names = "bclk";
1651 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1652 #iommu-cells = <1>;
1655 imgsys: clock-controller@15020000 {
1656 compatible = "mediatek,mt8192-imgsys";
1658 #clock-cells = <1>;
1662 compatible = "mediatek,mt8192-smi-larb";
1664 mediatek,larb-id = <9>;
1668 clock-names = "apb", "smi";
1669 power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
1672 imgsys2: clock-controller@15820000 {
1673 compatible = "mediatek,mt8192-imgsys2";
1675 #clock-cells = <1>;
1679 compatible = "mediatek,mt8192-smi-larb";
1681 mediatek,larb-id = <11>;
1685 clock-names = "apb", "smi";
1686 power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
1689 vcodec_dec: video-codec@16000000 {
1690 compatible = "mediatek,mt8192-vcodec-dec";
1694 #address-cells = <2>;
1695 #size-cells = <2>;
1698 video-codec@10000 {
1699 compatible = "mediatek,mtk-vcodec-lat";
1715 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
1716 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
1717 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
1718 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
1721 video-codec@25000 {
1722 compatible = "mediatek,mtk-vcodec-core";
1741 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
1742 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
1743 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
1744 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
1749 compatible = "mediatek,mt8192-smi-larb";
1751 mediatek,larb-id = <5>;
1755 clock-names = "apb", "smi";
1756 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
1759 vdecsys_soc: clock-controller@1600f000 {
1760 compatible = "mediatek,mt8192-vdecsys_soc";
1762 #clock-cells = <1>;
1766 compatible = "mediatek,mt8192-smi-larb";
1768 mediatek,larb-id = <4>;
1772 clock-names = "apb", "smi";
1773 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
1776 vdecsys: clock-controller@1602f000 {
1777 compatible = "mediatek,mt8192-vdecsys";
1779 #clock-cells = <1>;
1782 vencsys: clock-controller@17000000 {
1783 compatible = "mediatek,mt8192-vencsys";
1785 #clock-cells = <1>;
1789 compatible = "mediatek,mt8192-smi-larb";
1791 mediatek,larb-id = <7>;
1795 clock-names = "apb", "smi";
1796 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1800 compatible = "mediatek,mt8192-vcodec-enc";
1815 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1817 clock-names = "venc-set1";
1818 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1819 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
1822 camsys: clock-controller@1a000000 {
1823 compatible = "mediatek,mt8192-camsys";
1825 #clock-cells = <1>;
1829 compatible = "mediatek,mt8192-smi-larb";
1831 mediatek,larb-id = <13>;
1835 clock-names = "apb", "smi";
1836 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1840 compatible = "mediatek,mt8192-smi-larb";
1842 mediatek,larb-id = <14>;
1846 clock-names = "apb", "smi";
1847 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1851 compatible = "mediatek,mt8192-smi-larb";
1853 mediatek,larb-id = <16>;
1857 clock-names = "apb", "smi";
1858 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
1862 compatible = "mediatek,mt8192-smi-larb";
1864 mediatek,larb-id = <17>;
1868 clock-names = "apb", "smi";
1869 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
1873 compatible = "mediatek,mt8192-smi-larb";
1875 mediatek,larb-id = <18>;
1879 clock-names = "apb", "smi";
1880 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
1883 camsys_rawa: clock-controller@1a04f000 {
1884 compatible = "mediatek,mt8192-camsys_rawa";
1886 #clock-cells = <1>;
1889 camsys_rawb: clock-controller@1a06f000 {
1890 compatible = "mediatek,mt8192-camsys_rawb";
1892 #clock-cells = <1>;
1895 camsys_rawc: clock-controller@1a08f000 {
1896 compatible = "mediatek,mt8192-camsys_rawc";
1898 #clock-cells = <1>;
1901 ipesys: clock-controller@1b000000 {
1902 compatible = "mediatek,mt8192-ipesys";
1904 #clock-cells = <1>;
1908 compatible = "mediatek,mt8192-smi-larb";
1910 mediatek,larb-id = <20>;
1914 clock-names = "apb", "smi";
1915 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1919 compatible = "mediatek,mt8192-smi-larb";
1921 mediatek,larb-id = <19>;
1925 clock-names = "apb", "smi";
1926 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1929 mdpsys: clock-controller@1f000000 {
1930 compatible = "mediatek,mt8192-mdpsys";
1932 #clock-cells = <1>;
1936 compatible = "mediatek,mt8192-smi-larb";
1938 mediatek,larb-id = <2>;
1942 clock-names = "apb", "smi";
1943 power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
1947 thermal_zones: thermal-zones {
1948 cpu0-thermal {
1949 polling-delay = <1000>;
1950 polling-delay-passive = <250>;
1951 thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU0>;
1954 cpu0_alert: trip-alert {
1960 cpu0_crit: trip-crit {
1967 cooling-maps {
1970 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1978 cpu1-thermal {
1979 polling-delay = <1000>;
1980 polling-delay-passive = <250>;
1981 thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU1>;
1984 cpu1_alert: trip-alert {
1990 cpu1_crit: trip-crit {
1997 cooling-maps {
2000 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2008 cpu2-thermal {
2009 polling-delay = <1000>;
2010 polling-delay-passive = <250>;
2011 thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU2>;
2014 cpu2_alert: trip-alert {
2020 cpu2_crit: trip-crit {
2027 cooling-maps {
2030 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2038 cpu3-thermal {
2039 polling-delay = <1000>;
2040 polling-delay-passive = <250>;
2041 thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU3>;
2044 cpu3_alert: trip-alert {
2050 cpu3_crit: trip-crit {
2057 cooling-maps {
2060 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2068 cpu4-thermal {
2069 polling-delay = <1000>;
2070 polling-delay-passive = <250>;
2071 thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU0>;
2074 cpu4_alert: trip-alert {
2080 cpu4_crit: trip-crit {
2087 cooling-maps {
2090 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2098 cpu5-thermal {
2099 polling-delay = <1000>;
2100 polling-delay-passive = <250>;
2101 thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU1>;
2104 cpu5_alert: trip-alert {
2110 cpu5_crit: trip-crit {
2117 cooling-maps {
2120 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2128 cpu6-thermal {
2129 polling-delay = <1000>;
2130 polling-delay-passive = <250>;
2131 thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU2>;
2134 cpu6_alert: trip-alert {
2140 cpu6_crit: trip-crit {
2147 cooling-maps {
2150 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2158 cpu7-thermal {
2159 polling-delay = <1000>;
2160 polling-delay-passive = <250>;
2161 thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU3>;
2164 cpu7_alert: trip-alert {
2170 cpu7_crit: trip-crit {
2177 cooling-maps {
2180 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2188 vpu0-thermal {
2189 polling-delay = <1000>;
2190 polling-delay-passive = <250>;
2191 thermal-sensors = <&lvts_ap MT8192_AP_VPU0>;
2194 vpu0_alert: trip-alert {
2200 vpu0_crit: trip-crit {
2208 vpu1-thermal {
2209 polling-delay = <1000>;
2210 polling-delay-passive = <250>;
2211 thermal-sensors = <&lvts_ap MT8192_AP_VPU1>;
2214 vpu1_alert: trip-alert {
2220 vpu1_crit: trip-crit {
2228 gpu0-thermal {
2229 polling-delay = <1000>;
2230 polling-delay-passive = <250>;
2231 thermal-sensors = <&lvts_ap MT8192_AP_GPU0>;
2234 gpu0_alert: trip-alert {
2240 gpu0_crit: trip-crit {
2248 gpu1-thermal {
2249 polling-delay = <1000>;
2250 polling-delay-passive = <250>;
2251 thermal-sensors = <&lvts_ap MT8192_AP_GPU1>;
2254 gpu1_alert: trip-alert {
2260 gpu1_crit: trip-crit {
2268 infra-thermal {
2269 polling-delay = <1000>;
2270 polling-delay-passive = <250>;
2271 thermal-sensors = <&lvts_ap MT8192_AP_INFRA>;
2274 infra_alert: trip-alert {
2280 infra_crit: trip-crit {
2288 cam-thermal {
2289 polling-delay = <1000>;
2290 polling-delay-passive = <250>;
2291 thermal-sensors = <&lvts_ap MT8192_AP_CAM>;
2294 cam_alert: trip-alert {
2300 cam_crit: trip-crit {
2308 md0-thermal {
2309 polling-delay = <1000>;
2310 polling-delay-passive = <250>;
2311 thermal-sensors = <&lvts_ap MT8192_AP_MD0>;
2314 md0_alert: trip-alert {
2320 md0_crit: trip-crit {
2328 md1-thermal {
2329 polling-delay = <1000>;
2330 polling-delay-passive = <250>;
2331 thermal-sensors = <&lvts_ap MT8192_AP_MD1>;
2334 md1_alert: trip-alert {
2340 md1_crit: trip-crit {
2348 md2-thermal {
2349 polling-delay = <1000>;
2350 polling-delay-passive = <250>;
2351 thermal-sensors = <&lvts_ap MT8192_AP_MD2>;
2354 md2_alert: trip-alert {
2360 md2_crit: trip-crit {