Lines Matching +full:0 +full:x14006000
36 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #clock-cells = <0>;
59 #size-cells = <0>;
61 cpu0: cpu@0 {
64 reg = <0x000>;
75 performance-domains = <&performance 0>;
83 reg = <0x100>;
94 performance-domains = <&performance 0>;
102 reg = <0x200>;
113 performance-domains = <&performance 0>;
121 reg = <0x300>;
132 performance-domains = <&performance 0>;
140 reg = <0x400>;
159 reg = <0x500>;
178 reg = <0x600>;
197 reg = <0x700>;
275 arm,psci-suspend-param = <0x00010001>;
283 arm,psci-suspend-param = <0x00010001>;
291 arm,psci-suspend-param = <0x01010002>;
299 arm,psci-suspend-param = <0x01010002>;
328 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
329 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
330 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
331 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
335 gpu_opp_table: opp-table-0 {
424 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
429 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
439 reg = <0 0x0c000000 0 0x40000>,
440 <0 0x0c040000 0 0x200000>;
441 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
444 ppi_cluster0: interrupt-partition-0 {
455 reg = <0 0x10000000 0 0x1000>;
461 reg = <0 0x10001000 0 0x1000>;
468 reg = <0 0x10003000 0 0x1000>;
474 reg = <0 0x10005000 0 0x1000>,
475 <0 0x11c20000 0 0x1000>,
476 <0 0x11d10000 0 0x1000>,
477 <0 0x11d30000 0 0x1000>,
478 <0 0x11d40000 0 0x1000>,
479 <0 0x11e20000 0 0x1000>,
480 <0 0x11e70000 0 0x1000>,
481 <0 0x11ea0000 0 0x1000>,
482 <0 0x11f20000 0 0x1000>,
483 <0 0x11f30000 0 0x1000>,
484 <0 0x1000b000 0 0x1000>;
491 gpio-ranges = <&pio 0 0 220>;
493 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
499 reg = <0 0x10006000 0 0x1000>;
505 #size-cells = <0>;
516 #power-domain-cells = <0>;
524 #power-domain-cells = <0>;
533 #size-cells = <0>;
540 #size-cells = <0>;
545 #power-domain-cells = <0>;
550 #power-domain-cells = <0>;
555 #power-domain-cells = <0>;
560 #power-domain-cells = <0>;
565 #power-domain-cells = <0>;
577 clock-names = "disp", "disp-0", "disp-1", "disp-2",
581 #size-cells = <0>;
591 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
594 #power-domain-cells = <0>;
602 clock-names = "isp", "isp-0", "isp-1";
604 #power-domain-cells = <0>;
612 clock-names = "isp2", "isp2-0", "isp2-1";
614 #power-domain-cells = <0>;
621 clock-names = "mdp", "mdp-0";
623 #power-domain-cells = <0>;
630 clock-names = "venc", "venc-0";
632 #power-domain-cells = <0>;
641 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
644 #size-cells = <0>;
652 clock-names = "vdec2-0", "vdec2-1",
654 #power-domain-cells = <0>;
665 clock-names = "cam", "cam-0", "cam-1", "cam-2",
669 #size-cells = <0>;
675 clock-names = "cam_rawa-0";
676 #power-domain-cells = <0>;
682 clock-names = "cam_rawb-0";
683 #power-domain-cells = <0>;
689 clock-names = "cam_rawc-0";
690 #power-domain-cells = <0>;
699 reg = <0 0x10007000 0 0x100>;
705 reg = <0 0x1000c000 0 0x1000>;
712 reg = <0 0x10017000 0 0x1000>;
713 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
719 reg = <0 0x10026000 0 0x1000>;
721 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
731 reg = <0 0x10027000 0 0x000e00>,
732 <0 0x10029000 0 0x000100>;
746 reg = <0 0x10228000 0 0x4000>;
747 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
755 reg = <0 0x10720000 0 0x1000>;
764 reg = <0 0x11002000 0 0x1000>;
765 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
774 reg = <0 0x11003000 0 0x1000>;
775 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
783 reg = <0 0x11007000 0 0x1000>;
791 #size-cells = <0>;
792 reg = <0 0x1100a000 0 0x1000>;
793 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
803 reg = <0 0x1100b000 0 0xc00>;
804 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
814 reg = <0 0x1100bc00 0 0x400>;
815 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
826 reg = <0 0x1100e000 0 0x1000>;
827 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
839 #size-cells = <0>;
840 reg = <0 0x11010000 0 0x1000>;
841 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
853 #size-cells = <0>;
854 reg = <0 0x11012000 0 0x1000>;
855 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
867 #size-cells = <0>;
868 reg = <0 0x11013000 0 0x1000>;
869 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
881 #size-cells = <0>;
882 reg = <0 0x11018000 0 0x1000>;
883 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
895 #size-cells = <0>;
896 reg = <0 0x11019000 0 0x1000>;
897 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
909 #size-cells = <0>;
910 reg = <0 0x1101d000 0 0x1000>;
911 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
923 #size-cells = <0>;
924 reg = <0 0x1101e000 0 0x1000>;
925 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
935 reg = <0 0x10500000 0 0x100000>,
936 <0 0x10720000 0 0xe0000>,
937 <0 0x10700000 0 0x8000>;
939 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
948 reg = <0 0x11200000 0 0x1000>,
949 <0 0x11203e00 0 0x0100>;
951 interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
967 mediatek,syscon-wakeup = <&pericfg 0x420 102>;
973 reg = <0 0x11210000 0 0x2000>;
978 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
1103 reg = <0 0x11230000 0 0x2000>;
1117 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
1118 bus-range = <0x00 0xff>;
1119 ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
1120 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
1122 interrupt-map-mask = <0 0 0 7>;
1123 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1124 <0 0 0 2 &pcie_intc0 1>,
1125 <0 0 0 3 &pcie_intc0 2>,
1126 <0 0 0 4 &pcie_intc0 3>;
1130 #address-cells = <0>;
1137 reg = <0 0x11234000 0 0xe0>;
1138 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
1146 #size-cells = <0>;
1152 reg = <0 0x11278000 0 0x1000>;
1153 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
1163 reg = <0 0x11c10000 0 0x1000>;
1168 reg = <0x1c0 0x58>;
1172 reg = <0x580 0x68>;
1178 reg = <0 0x11cb0000 0 0x1000>,
1179 <0 0x10217300 0 0x80>;
1180 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1186 #size-cells = <0>;
1192 reg = <0 0x11cb1000 0 0x1000>;
1198 reg = <0 0x11d00000 0 0x1000>,
1199 <0 0x10217600 0 0x180>;
1200 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1206 #size-cells = <0>;
1212 reg = <0 0x11d01000 0 0x1000>,
1213 <0 0x10217780 0 0x180>;
1214 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1220 #size-cells = <0>;
1226 reg = <0 0x11d02000 0 0x1000>,
1227 <0 0x10217900 0 0x180>;
1228 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
1234 #size-cells = <0>;
1240 reg = <0 0x11d03000 0 0x1000>;
1246 reg = <0 0x11d20000 0 0x1000>,
1247 <0 0x10217100 0 0x80>;
1248 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1254 #size-cells = <0>;
1260 reg = <0 0x11d21000 0 0x1000>,
1261 <0 0x10217180 0 0x180>;
1262 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1268 #size-cells = <0>;
1274 reg = <0 0x11d22000 0 0x1000>,
1275 <0 0x10217380 0 0x180>;
1276 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1282 #size-cells = <0>;
1288 reg = <0 0x11d23000 0 0x1000>;
1294 reg = <0 0x11e00000 0 0x1000>,
1295 <0 0x10217500 0 0x80>;
1296 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1302 #size-cells = <0>;
1308 reg = <0 0x11e01000 0 0x1000>;
1317 ranges = <0x0 0x0 0x11e40000 0x1000>;
1319 u2port0: usb-phy@0 {
1320 reg = <0x0 0x700>;
1327 reg = <0x700 0x900>;
1336 reg = <0 0x11e50000 0 0x1000>;
1338 #clock-cells = <0>;
1339 #phy-cells = <0>;
1346 reg = <0 0x11f00000 0 0x1000>,
1347 <0 0x10217080 0 0x80>;
1348 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
1354 #size-cells = <0>;
1360 reg = <0 0x11f01000 0 0x1000>,
1361 <0 0x10217580 0 0x80>;
1362 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1368 #size-cells = <0>;
1374 reg = <0 0x11f02000 0 0x1000>;
1380 reg = <0 0x11f10000 0 0x1000>;
1386 reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
1387 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
1402 reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
1403 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
1418 reg = <0 0x13000000 0 0x4000>;
1419 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>,
1420 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>,
1421 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
1440 reg = <0 0x13fbf000 0 0x1000>;
1446 reg = <0 0x14000000 0 0x1000>;
1449 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1451 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1456 reg = <0 0x14001000 0 0x1000>;
1457 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
1466 reg = <0 0x14002000 0 0x1000>;
1477 reg = <0 0x14003000 0 0x1000>;
1478 mediatek,larb-id = <0>;
1487 reg = <0 0x14004000 0 0x1000>;
1497 reg = <0 0x14005000 0 0x1000>;
1498 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
1503 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1508 reg = <0 0x14006000 0 0x1000>;
1509 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
1514 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1520 reg = <0 0x14007000 0 0x1000>;
1521 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
1526 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1532 reg = <0 0x14009000 0 0x1000>;
1533 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
1536 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1541 reg = <0 0x1400a000 0 0x1000>;
1542 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
1545 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1551 reg = <0 0x1400b000 0 0x1000>;
1552 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
1555 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1561 reg = <0 0x1400c000 0 0x1000>;
1562 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
1565 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1570 reg = <0 0x1400d000 0 0x1000>;
1571 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
1574 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1580 reg = <0 0x1400e000 0 0x1000>;
1581 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
1584 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1589 reg = <0 0x14010000 0 0x1000>;
1590 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
1608 reg = <0 0x14014000 0 0x1000>;
1609 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
1614 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1620 reg = <0 0x14015000 0 0x1000>;
1621 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
1626 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1631 reg = <0 0x14016000 0 0x1000>;
1632 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
1642 reg = <0 0x1401d000 0 0x1000>;
1648 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
1657 reg = <0 0x15020000 0 0x1000>;
1663 reg = <0 0x1502e000 0 0x1000>;
1674 reg = <0 0x15820000 0 0x1000>;
1680 reg = <0 0x1582e000 0 0x1000>;
1691 reg = <0 0x16000000 0 0x1000>;
1696 ranges = <0 0 0 0x16000000 0 0x26000>;
1700 reg = <0x0 0x10000 0 0x800>;
1701 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
1723 reg = <0 0x25000 0 0x1000>;
1724 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
1750 reg = <0 0x1600d000 0 0x1000>;
1761 reg = <0 0x1600f000 0 0x1000>;
1767 reg = <0 0x1602e000 0 0x1000>;
1778 reg = <0 0x1602f000 0 0x1000>;
1784 reg = <0 0x17000000 0 0x1000>;
1790 reg = <0 0x17010000 0 0x1000>;
1801 reg = <0 0x17020000 0 0x2000>;
1813 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
1824 reg = <0 0x1a000000 0 0x1000>;
1830 reg = <0 0x1a001000 0 0x1000>;
1841 reg = <0 0x1a002000 0 0x1000>;
1852 reg = <0 0x1a00f000 0 0x1000>;
1863 reg = <0 0x1a010000 0 0x1000>;
1874 reg = <0 0x1a011000 0 0x1000>;
1885 reg = <0 0x1a04f000 0 0x1000>;
1891 reg = <0 0x1a06f000 0 0x1000>;
1897 reg = <0 0x1a08f000 0 0x1000>;
1903 reg = <0 0x1b000000 0 0x1000>;
1909 reg = <0 0x1b00f000 0 0x1000>;
1920 reg = <0 0x1b10f000 0 0x1000>;
1931 reg = <0 0x1f000000 0 0x1000>;
1937 reg = <0 0x1f002000 0 0x1000>;