Lines Matching +full:0 +full:x1400d000
327 #size-cells = <0>;
365 cpu0: cpu@0 {
368 reg = <0x000>;
392 reg = <0x100>;
416 reg = <0x200>;
440 reg = <0x300>;
464 reg = <0x400>;
488 reg = <0x500>;
512 reg = <0x600>;
536 reg = <0x700>;
562 arm,psci-suspend-param = <0x00010001>;
571 arm,psci-suspend-param = <0x00010001>;
580 arm,psci-suspend-param = <0x01010001>;
589 arm,psci-suspend-param = <0x01010001>;
629 #clock-cells = <0>;
638 #clock-cells = <0>;
645 #clock-cells = <0>;
656 opp-supported-hw = <0xff>;
662 opp-supported-hw = <0xff>;
668 opp-supported-hw = <0xff>;
674 opp-supported-hw = <0xff>;
680 opp-supported-hw = <0xff>;
686 opp-supported-hw = <0xff>;
692 opp-supported-hw = <0xff>;
698 opp-supported-hw = <0xff>;
704 opp-supported-hw = <0xff>;
710 opp-supported-hw = <0xff>;
716 opp-supported-hw = <0xff>;
722 opp-supported-hw = <0xff>;
728 opp-supported-hw = <0xff>;
734 opp-supported-hw = <0x8>;
740 opp-supported-hw = <0x10>;
746 opp-supported-hw = <0x30>;
752 opp-supported-hw = <0x8>;
758 opp-supported-hw = <0x10>;
764 opp-supported-hw = <0x30>;
770 opp-supported-hw = <0x8>;
776 opp-supported-hw = <0x10>;
782 opp-supported-hw = <0x30>;
806 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
807 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
808 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
809 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
816 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
825 reg = <0 0x0c000000 0 0x40000>,
826 <0 0x0c040000 0 0x200000>;
827 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
830 ppi_cluster0: interrupt-partition-0 {
842 reg = <0 0xc53a000 0 0x1000>;
848 reg = <0 0x10000000 0 0x1000>;
854 reg = <0 0x10001000 0 0x1000>;
861 reg = <0 0x10003000 0 0x1000>;
866 reg = <0 0x10005000 0 0x1000>,
867 <0 0x10002000 0 0x0200>,
868 <0 0x10002200 0 0x0200>,
869 <0 0x10002400 0 0x0200>,
870 <0 0x10002600 0 0x0200>,
871 <0 0x10002a00 0 0x0200>,
872 <0 0x10002c00 0 0x0200>,
873 <0 0x1000b000 0 0x1000>;
878 gpio-ranges = <&pio 0 0 185>;
880 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
886 reg = <0 0x10006000 0 0x1000>;
892 #size-cells = <0>;
901 #size-cells = <0>;
908 #size-cells = <0>;
913 #power-domain-cells = <0>;
918 #power-domain-cells = <0>;
929 #power-domain-cells = <0>;
934 #power-domain-cells = <0>;
939 #power-domain-cells = <0>;
949 #size-cells = <0>;
955 #size-cells = <0>;
961 #power-domain-cells = <0>;
969 #power-domain-cells = <0>;
987 #size-cells = <0>;
996 #power-domain-cells = <0>;
1014 #size-cells = <0>;
1019 #power-domain-cells = <0>;
1024 #power-domain-cells = <0>;
1035 #size-cells = <0>;
1040 #power-domain-cells = <0>;
1057 #power-domain-cells = <0>;
1066 #power-domain-cells = <0>;
1078 #power-domain-cells = <0>;
1087 reg = <0 0x10007000 0 0x1000>;
1093 reg = <0 0x1000c000 0 0x1000>;
1099 reg = <0 0x1000d000 0 0x1000>;
1101 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1109 reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>;
1117 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>,
1118 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>;
1125 reg = <0 0x10017000 0 0x1000>;
1126 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>;
1132 reg = <0 0X1022c000 0 0x4000>;
1135 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
1141 reg = <0 0x10500000 0 0x40000>,
1142 <0 0x105c0000 0 0x19080>;
1144 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1149 reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>,
1150 <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>;
1165 #mbox-cells = <0>;
1166 reg = <0 0x10686100 0 0x1000>;
1167 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
1172 #mbox-cells = <0>;
1173 reg = <0 0x10687100 0 0x1000>;
1174 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>;
1179 reg = <0 0x11000000 0 0x1000>;
1187 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>;
1193 reg = <0 0x11001000 0 0x1000>;
1202 reg = <0 0x11002000 0 0x1000>;
1203 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
1212 reg = <0 0x11003000 0 0x1000>;
1213 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1221 reg = <0 0x11007000 0 0x1000>,
1222 <0 0x10200100 0 0x100>;
1223 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
1229 #size-cells = <0>;
1235 reg = <0 0x11008000 0 0x1000>,
1236 <0 0x10200200 0 0x100>;
1237 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1243 #size-cells = <0>;
1249 reg = <0 0x11009000 0 0x1000>,
1250 <0 0x10200300 0 0x180>;
1251 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>;
1257 #size-cells = <0>;
1263 reg = <0 0x1100f000 0 0x1000>,
1264 <0 0x10200480 0 0x100>;
1265 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
1271 #size-cells = <0>;
1277 reg = <0 0x11011000 0 0x1000>,
1278 <0 0x10200580 0 0x180>;
1279 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
1285 #size-cells = <0>;
1291 reg = <0 0x11016000 0 0x1000>,
1292 <0 0x10200700 0 0x100>;
1293 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
1299 #size-cells = <0>;
1305 reg = <0 0x1100d000 0 0x1000>,
1306 <0 0x10200800 0 0x100>;
1307 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
1313 #size-cells = <0>;
1319 reg = <0 0x11004000 0 0x1000>,
1320 <0 0x10200900 0 0x180>;
1321 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
1327 #size-cells = <0>;
1333 reg = <0 0x11005000 0 0x1000>,
1334 <0 0x10200A80 0 0x180>;
1335 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1341 #size-cells = <0>;
1348 #size-cells = <0>;
1349 reg = <0 0x1100a000 0 0x1000>;
1350 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
1360 reg = <0 0x1100e000 0 0x1000>;
1361 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1372 #size-cells = <0>;
1373 reg = <0 0x11010000 0 0x1000>;
1374 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>;
1385 #size-cells = <0>;
1386 reg = <0 0x11012000 0 0x1000>;
1387 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>;
1398 #size-cells = <0>;
1399 reg = <0 0x11013000 0 0x1000>;
1400 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
1411 #size-cells = <0>;
1412 reg = <0 0x11014000 0 0x1000>;
1413 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1424 #size-cells = <0>;
1425 reg = <0 0x11015000 0 0x1000>;
1426 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1436 reg = <0 0x11017000 0 0x1000>;
1443 reg = <0 0x11018000 0 0x1000>;
1444 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>;
1452 reg = <0 0x11019000 0 0x1000>,
1453 <0 0x10200c00 0 0x180>;
1454 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
1460 #size-cells = <0>;
1466 reg = <0 0x11210000 0 0x2000>;
1517 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1528 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
1535 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
1545 reg = <0 0x11200000 0 0x1000>;
1553 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
1554 mediatek,syscon-wakeup = <&pericfg 0x420 2>;
1563 reg = <0 0x11230000 0 0x10000>,
1564 <0 0x11cd0000 0 0x1000>;
1570 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
1579 reg = <0 0x11240000 0 0x1000>,
1580 <0 0x11c90000 0 0x1000>;
1585 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
1593 reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>;
1600 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
1610 reg = <0 0x11280000 0 0x1000>;
1618 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
1619 mediatek,syscon-wakeup = <&pericfg 0x424 2>;
1630 ranges = <0x0 0x0 0x11c80000 0x1000>;
1633 u2port1: usb-phy@0 {
1634 reg = <0x0 0x700>;
1641 reg = <0x700 0x900>;
1653 ranges = <0x0 0x0 0x11ca0000 0x1000>;
1656 u2port0: usb-phy@0 {
1657 reg = <0x0 0x700>;
1661 mediatek,discth = <0x8>;
1667 reg = <0 0x11cb0000 0 0x1000>;
1672 reg = <0x59c 0x4>;
1673 bits = <0 3>;
1679 reg = <0 0x11cc0000 0 0x1000>;
1681 #clock-cells = <0>;
1682 #phy-cells = <0>;
1689 reg = <0 0x13000000 0 0x1000>;
1696 reg = <0 0x13040000 0 0x4000>;
1699 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>,
1700 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
1701 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
1716 reg = <0 0x14000000 0 0x1000>;
1719 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1721 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1726 reg = <0 0x14001000 0 0x1000>;
1728 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
1729 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1737 reg = <0 0x14002000 0 0x1000>;
1746 reg = <0 0x14003000 0 0x1000>;
1750 mediatek,larb-id = <0>;
1757 reg = <0 0x14004000 0 0x1000>;
1768 reg = <0 0x14005000 0 0x1000>;
1770 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
1772 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1778 reg = <0 0x14006000 0 0x1000>;
1780 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
1782 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1788 reg = <0 0x14007000 0 0x1000>;
1790 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
1792 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1798 reg = <0 0x14009000 0 0x1000>;
1800 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>;
1801 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1807 reg = <0 0x1400a000 0 0x1000>;
1814 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
1824 reg = <0 0x1400b000 0 0x1000>;
1826 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>;
1827 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1833 reg = <0 0x1400c000 0 0x1000>;
1835 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>;
1836 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1842 reg = <0 0x1400d000 0 0x1000>;
1844 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
1845 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1852 reg = <0 0x1400e000 0 0x1000>;
1854 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
1855 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1861 reg = <0 0x1400f000 0 0x1000>;
1863 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>;
1864 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1870 reg = <0 0x14013000 0 0x1000>;
1875 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>;
1889 reg = <0 0x14016000 0 0x1000>;
1892 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>;
1903 reg = <0 0x1401f000 0 0x1000>;
1905 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>;
1907 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>;
1913 reg = <0 0x14020000 0 0x1000>;
1919 reg = <0 0x14023000 0 0x1000>;
1930 reg = <0 0x15020000 0 0x1000>;
1936 reg = <0 0x1502e000 0 0x1000>;
1947 reg = <0 0x15820000 0 0x1000>;
1953 reg = <0 0x1582e000 0 0x1000>;
1964 reg = <0 0x1602e000 0 0x1000>;
1975 reg = <0 0x1602f000 0 0x1000>;
1981 reg = <0 0x17000000 0 0x1000>;
1987 reg = <0 0x17010000 0 0x1000>;
1998 reg = <0 0x1a000000 0 0x1000>;
2004 reg = <0 0x1a001000 0 0x1000>;
2014 reg = <0 0x1a002000 0 0x1000>;
2024 reg = <0 0x1a00f000 0 0x1000>;
2035 reg = <0 0x1a010000 0 0x1000>;
2046 reg = <0 0x1a04f000 0 0x1000>;
2052 reg = <0 0x1a06f000 0 0x1000>;
2058 reg = <0 0x1b000000 0 0x1000>;
2064 reg = <0 0x1b002000 0 0x1000>;
2074 reg = <0 0x1c000000 0 0x1000>;
2080 reg = <0 0x1c00f000 0 0x1000>;
2090 reg = <0 0x1c10f000 0 0x1000>;