Lines Matching +full:0 +full:x11007000
293 #size-cells = <0>;
327 cpu0: cpu@0 {
330 reg = <0x000>;
353 reg = <0x001>;
376 reg = <0x002>;
399 reg = <0x003>;
422 reg = <0x100>;
445 reg = <0x101>;
468 reg = <0x102>;
491 reg = <0x103>;
517 arm,psci-suspend-param = <0x00010001>;
523 CLUSTER_SLEEP0: cluster-sleep-0 {
526 arm,psci-suspend-param = <0x01010001>;
534 arm,psci-suspend-param = <0x01010001>;
560 gpu_opp_table: opp-table-0 {
664 #clock-cells = <0>;
673 #clock-cells = <0>;
681 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
682 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
683 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
684 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
696 reg = <0 0x08000000 0 0x0010>;
707 reg = <0 0x0c000000 0 0x40000>, /* GICD */
708 <0 0x0c100000 0 0x200000>, /* GICR */
709 <0 0x0c400000 0 0x2000>, /* GICC */
710 <0 0x0c410000 0 0x1000>, /* GICH */
711 <0 0x0c420000 0 0x2000>; /* GICV */
713 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
715 ppi_cluster0: interrupt-partition-0 {
726 reg = <0 0x0c530000 0 0x1000>;
736 reg = <0 0x0c530a80 0 0x50>;
741 reg = <0x0 0xd410000 0x0 0x1000>;
749 reg = <0x0 0xd510000 0x0 0x1000>;
757 reg = <0x0 0xd610000 0x0 0x1000>;
765 reg = <0x0 0xd710000 0x0 0x1000>;
773 reg = <0x0 0xd810000 0x0 0x1000>;
781 reg = <0x0 0xd910000 0x0 0x1000>;
789 reg = <0x0 0xda10000 0x0 0x1000>;
797 reg = <0x0 0xdb10000 0x0 0x1000>;
805 reg = <0 0x10000000 0 0x1000>;
811 reg = <0 0x10001000 0 0x1000>;
818 reg = <0 0x10003000 0 0x1000>;
824 reg = <0 0x10005000 0 0x1000>,
825 <0 0x11f20000 0 0x1000>,
826 <0 0x11e80000 0 0x1000>,
827 <0 0x11e70000 0 0x1000>,
828 <0 0x11e90000 0 0x1000>,
829 <0 0x11d30000 0 0x1000>,
830 <0 0x11d20000 0 0x1000>,
831 <0 0x11c50000 0 0x1000>,
832 <0 0x11f30000 0 0x1000>,
833 <0 0x1000b000 0 0x1000>;
840 gpio-ranges = <&pio 0 0 192>;
848 reg = <0 0x10006000 0 0x1000>;
854 #size-cells = <0>;
864 #power-domain-cells = <0>;
870 #power-domain-cells = <0>;
878 #size-cells = <0>;
884 #size-cells = <0>;
889 #power-domain-cells = <0>;
894 #power-domain-cells = <0>;
900 #power-domain-cells = <0>;
918 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
924 #size-cells = <0>;
937 clock-names = "cam", "cam-0", "cam-1",
942 #power-domain-cells = <0>;
950 clock-names = "isp", "isp-0", "isp-1";
953 #power-domain-cells = <0>;
959 #power-domain-cells = <0>;
965 #power-domain-cells = <0>;
978 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
983 #size-cells = <0>;
991 #power-domain-cells = <0>;
999 #power-domain-cells = <0>;
1008 reg = <0 0x10007000 0 0x100>;
1014 reg = <0 0x1000c000 0 0x1000>;
1020 reg = <0 0x1000d000 0 0x1000>;
1030 reg = <0 0x10010000 0 0x1000>;
1039 reg = <0 0x10500000 0 0x80000>,
1040 <0 0x105c0000 0 0x19080>;
1052 reg = <0 0x10017000 0 0x1000>;
1059 reg = <0 0x10205000 0 0x1000>;
1068 reg = <0 0x10238000 0 0x4000>;
1078 reg = <0 0x11001000 0 0x1000>;
1088 reg = <0 0x11002000 0 0x1000>;
1098 reg = <0 0x11003000 0 0x1000>;
1108 reg = <0 0x11004000 0 0x1000>;
1117 reg = <0 0x11005000 0 0x1000>,
1118 <0 0x11000600 0 0x80>;
1125 #size-cells = <0>;
1131 reg = <0 0x11007000 0 0x1000>,
1132 <0 0x11000080 0 0x80>;
1139 #size-cells = <0>;
1145 reg = <0 0x11008000 0 0x1000>,
1146 <0 0x11000100 0 0x80>;
1154 #size-cells = <0>;
1160 reg = <0 0x11009000 0 0x1000>,
1161 <0 0x11000280 0 0x80>;
1169 #size-cells = <0>;
1176 #size-cells = <0>;
1177 reg = <0 0x1100a000 0 0x1000>;
1189 reg = <0 0x1100b000 0 0xc00>;
1194 interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>;
1203 reg = <0 0x1100bc00 0 0x400>;
1215 reg = <0 0x1100e000 0 0x1000>;
1226 reg = <0 0x11006000 0 0x1000>;
1240 reg = <0 0x1100f000 0 0x1000>,
1241 <0 0x11000400 0 0x80>;
1248 #size-cells = <0>;
1255 #size-cells = <0>;
1256 reg = <0 0x11010000 0 0x1000>;
1267 reg = <0 0x11011000 0 0x1000>,
1268 <0 0x11000480 0 0x80>;
1275 #size-cells = <0>;
1282 #size-cells = <0>;
1283 reg = <0 0x11012000 0 0x1000>;
1295 #size-cells = <0>;
1296 reg = <0 0x11013000 0 0x1000>;
1307 reg = <0 0x11014000 0 0x1000>,
1308 <0 0x11000180 0 0x80>;
1316 #size-cells = <0>;
1322 reg = <0 0x11015000 0 0x1000>,
1323 <0 0x11000300 0 0x80>;
1331 #size-cells = <0>;
1337 reg = <0 0x11016000 0 0x1000>,
1338 <0 0x11000500 0 0x80>;
1346 #size-cells = <0>;
1352 reg = <0 0x11017000 0 0x1000>,
1353 <0 0x11000580 0 0x80>;
1361 #size-cells = <0>;
1368 #size-cells = <0>;
1369 reg = <0 0x11018000 0 0x1000>;
1381 #size-cells = <0>;
1382 reg = <0 0x11019000 0 0x1000>;
1393 reg = <0 0x1101a000 0 0x1000>,
1394 <0 0x11000680 0 0x80>;
1401 #size-cells = <0>;
1407 reg = <0 0x1101b000 0 0x1000>,
1408 <0 0x11000700 0 0x80>;
1415 #size-cells = <0>;
1421 reg = <0 0x11201000 0 0x2e00>,
1422 <0 0x11203e00 0 0x0100>;
1430 mediatek,syscon-wakeup = <&pericfg 0x420 101>;
1439 reg = <0 0x11200000 0 0x1000>;
1451 reg = <0 0x11220000 0 0x1000>;
1549 reg = <0 0x11230000 0 0x1000>,
1550 <0 0x11f50000 0 0x1000>;
1561 reg = <0 0x11240000 0 0x1000>,
1562 <0 0x11e10000 0 0x1000>;
1573 reg = <0 0x11e50000 0 0x1000>;
1575 #clock-cells = <0>;
1576 #phy-cells = <0>;
1585 reg = <0 0x11f10000 0 0x1000>;
1589 reg = <0x180 0xc>;
1593 reg = <0x190 0xc>;
1597 reg = <0x580 0x64>;
1606 ranges = <0 0 0x11f40000 0x1000>;
1609 u2port0: usb-phy@0 {
1610 reg = <0x0 0x700>;
1619 reg = <0x0700 0x900>;
1629 reg = <0 0x13000000 0 0x1000>;
1635 reg = <0 0x13040000 0 0x4000>;
1655 reg = <0 0x14000000 0 0x1000>;
1658 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1660 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1665 reg = <0 0x14001000 0 0x1000>;
1666 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1673 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
1674 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
1680 reg = <0 0x14003000 0 0x1000>;
1681 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
1689 reg = <0 0x14004000 0 0x1000>;
1690 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
1698 reg = <0 0x14005000 0 0x1000>;
1699 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1710 reg = <0 0x14006000 0 0x1000>;
1711 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1721 reg = <0 0x14008000 0 0x1000>;
1726 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1731 reg = <0 0x14009000 0 0x1000>;
1736 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1741 reg = <0 0x1400a000 0 0x1000>;
1746 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1751 reg = <0 0x1400b000 0 0x1000>;
1757 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1762 reg = <0 0x1400c000 0 0x1000>;
1768 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1774 reg = <0 0x1400e000 0 0x1000>;
1778 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1783 reg = <0 0x1400f000 0 0x1000>;
1787 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1792 reg = <0 0x14010000 0 0x1000>;
1796 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1801 reg = <0 0x14011000 0 0x1000>;
1805 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1810 reg = <0 0x14012000 0 0x1000>;
1814 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1819 reg = <0 0x14014000 0 0x1000>;
1833 reg = <0 0x14016000 0 0x1000>;
1838 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1843 reg = <0 0x14017000 0 0x1000>;
1853 reg = <0 0x14019000 0 0x1000>;
1864 reg = <0 0x1401c000 0 0x1000>;
1865 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
1873 reg = <0 0x15020000 0 0x1000>;
1879 reg = <0 0x15021000 0 0x1000>;
1889 reg = <0 0x1502f000 0 0x1000>;
1899 reg = <0 0x16000000 0 0x1000>;
1905 reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */
1906 <0 0x16021000 0 0x800>, /* VDEC_VLD */
1907 <0 0x16021800 0 0x800>, /* VDEC_TOP */
1908 <0 0x16022000 0 0x1000>, /* VDEC_MC */
1909 <0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */
1910 <0 0x16024000 0 0x1000>, /* VDEC_AVCMV */
1911 <0 0x16025000 0 0x1000>, /* VDEC_PP */
1912 <0 0x16026800 0 0x800>, /* VP8_VD */
1913 <0 0x16027000 0 0x800>, /* VP6_VD */
1914 <0 0x16027800 0 0x800>, /* VP8_VL */
1915 <0 0x16028400 0 0x400>; /* VP9_VD */
1935 reg = <0 0x16010000 0 0x1000>;
1944 reg = <0 0x17000000 0 0x1000>;
1950 reg = <0 0x17010000 0 0x1000>;
1960 reg = <0 0x17030000 0 0x1000>;
1971 reg = <0 0x19000000 0 0x1000>;
1977 reg = <0 0x19010000 0 0x1000>;
1983 reg = <0 0x19180000 0 0x1000>;
1989 reg = <0 0x19280000 0 0x1000>;
1995 reg = <0 0x1a000000 0 0x1000>;
2001 reg = <0 0x1a001000 0 0x1000>;
2011 reg = <0 0x1a002000 0 0x1000>;
2024 thermal-sensors = <&thermal 0>;
2087 polling-delay-passive = <0>;
2088 polling-delay = <0>;
2096 polling-delay-passive = <0>;
2097 polling-delay = <0>;
2105 polling-delay-passive = <0>;
2106 polling-delay = <0>;
2114 polling-delay-passive = <0>;
2115 polling-delay = <0>;
2123 polling-delay-passive = <0>;
2124 polling-delay = <0>;
2132 polling-delay-passive = <0>;
2133 polling-delay = <0>;