Lines Matching +full:pinmux +full:-
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
14 chassis-type = "embedded";
15 compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
27 stdout-path = "serial0:921600n8";
30 reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
35 compatible = "shared-dma-pool";
37 no-map;
41 thermal-sensor {
43 pullup-uv = <1800000>;
44 pullup-ohm = <390000>;
45 pulldown-ohm = <0>;
46 io-channels = <&auxadc 0>;
55 mali-supply = <&mt6358_vgpu_reg>;
59 pinctrl-names = "default";
60 pinctrl-0 = <&i2c_pins_0>;
62 clock-frequency = <100000>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&i2c_pins_1>;
69 clock-frequency = <100000>;
73 pinctrl-names = "default";
74 pinctrl-0 = <&i2c_pins_2>;
76 clock-frequency = <100000>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&i2c_pins_3>;
83 clock-frequency = <100000>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&i2c_pins_4>;
90 clock-frequency = <1000000>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&i2c_pins_5>;
97 clock-frequency = <1000000>;
102 pinctrl-names = "default", "state_uhs";
103 pinctrl-0 = <&mmc0_pins_default>;
104 pinctrl-1 = <&mmc0_pins_uhs>;
105 bus-width = <8>;
106 max-frequency = <200000000>;
107 cap-mmc-highspeed;
108 mmc-hs200-1_8v;
109 mmc-hs400-1_8v;
110 cap-mmc-hw-reset;
111 no-sdio;
112 no-sd;
113 hs400-ds-delay = <0x12814>;
114 vmmc-supply = <&mt6358_vemc_reg>;
115 vqmmc-supply = <&mt6358_vio18_reg>;
116 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
117 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
118 non-removable;
123 pinctrl-names = "default", "state_uhs";
124 pinctrl-0 = <&mmc1_pins_default>;
125 pinctrl-1 = <&mmc1_pins_uhs>;
126 bus-width = <4>;
127 max-frequency = <200000000>;
128 cap-sd-highspeed;
129 sd-uhs-sdr50;
130 sd-uhs-sdr104;
131 cap-sdio-irq;
132 no-mmc;
133 no-sd;
134 vmmc-supply = <&mt6358_vmch_reg>;
135 vqmmc-supply = <&mt6358_vmc_reg>;
136 keep-power-in-suspend;
137 wakeup-source;
138 non-removable;
142 regulator-min-microvolt = <625000>;
143 regulator-max-microvolt = <900000>;
145 regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
146 regulator-coupled-max-spread = <100000>;
150 regulator-min-microvolt = <850000>;
151 regulator-max-microvolt = <1000000>;
153 regulator-coupled-with = <&mt6358_vgpu_reg>;
154 regulator-coupled-max-spread = <100000>;
160 pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
162 mediatek,pull-up-adv = <3>;
163 mediatek,drive-strength-adv = <00>;
169 pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
171 mediatek,pull-up-adv = <3>;
172 mediatek,drive-strength-adv = <00>;
178 pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
180 mediatek,pull-up-adv = <3>;
181 mediatek,drive-strength-adv = <00>;
187 pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
189 mediatek,pull-up-adv = <3>;
190 mediatek,drive-strength-adv = <00>;
196 pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
198 mediatek,pull-up-adv = <3>;
199 mediatek,drive-strength-adv = <00>;
205 pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
207 mediatek,pull-up-adv = <3>;
208 mediatek,drive-strength-adv = <00>;
214 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
218 bias-disable;
224 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
233 input-enable;
234 bias-pull-up;
238 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
239 bias-pull-down;
243 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
244 bias-pull-up;
250 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
259 input-enable;
260 drive-strength = <MTK_DRIVE_10mA>;
261 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
265 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
266 drive-strength = <MTK_DRIVE_10mA>;
267 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
271 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
272 drive-strength = <MTK_DRIVE_10mA>;
273 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
277 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
278 drive-strength = <MTK_DRIVE_10mA>;
279 bias-pull-up;
285 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
290 input-enable;
291 bias-pull-up;
295 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
296 input-enable;
297 bias-pull-down;
301 pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
303 output-high;
309 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
314 drive-strength = <MTK_DRIVE_6mA>;
315 input-enable;
316 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
320 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
321 drive-strength = <MTK_DRIVE_6mA>;
322 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
323 input-enable;
329 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
333 bias-disable;
339 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
343 bias-disable;
349 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
353 bias-disable;
359 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
363 bias-disable;
369 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
373 bias-disable;
379 pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
385 interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
389 domain-supply = <&mt6358_vgpu_reg>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&spi_pins_0>;
395 mediatek,pad-select = <0>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&spi_pins_1>;
402 mediatek,pad-select = <0>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&spi_pins_2>;
409 mediatek,pad-select = <0>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&spi_pins_3>;
416 mediatek,pad-select = <0>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&spi_pins_4>;
423 mediatek,pad-select = <0>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&spi_pins_5>;
430 mediatek,pad-select = <0>;
436 proc-supply = <&mt6358_vproc12_reg>;
440 proc-supply = <&mt6358_vproc12_reg>;
444 proc-supply = <&mt6358_vproc12_reg>;
448 proc-supply = <&mt6358_vproc12_reg>;
452 proc-supply = <&mt6358_vproc12_reg>;
456 proc-supply = <&mt6358_vproc11_reg>;
460 proc-supply = <&mt6358_vproc11_reg>;
464 proc-supply = <&mt6358_vproc11_reg>;
468 proc-supply = <&mt6358_vproc11_reg>;
477 pinctrl-0 = <&pwm_pins_1>;
478 pinctrl-names = "default";