Lines Matching +full:0 +full:x10209100
53 cluster0_opp: opp-table-0 {
129 #size-cells = <0>;
151 cpu0: cpu@0 {
154 reg = <0x000>;
169 reg = <0x001>;
184 reg = <0x100>;
199 reg = <0x101>;
214 CPU_SLEEP_0: cpu-sleep-0 {
220 arm,psci-suspend-param = <0x0010000>;
242 cpu_suspend = <0x84000001>;
243 cpu_off = <0x84000002>;
244 cpu_on = <0x84000003>;
249 #clock-cells = <0>;
256 #clock-cells = <0>;
263 #clock-cells = <0>;
264 clock-frequency = <0>;
323 reg = <0 0xb7000000 0 0x500000>;
324 alignment = <0x1000>;
351 reg = <0 0x10000000 0 0x1000>;
357 reg = <0 0x10001000 0 0x1000>;
364 reg = <0 0x10003000 0 0x1000>;
371 reg = <0 0x10005000 0 0x1000>;
376 reg = <0 0x1000b000 0 0x1000>;
447 reg = <0 0x10006000 0 0x1000>;
453 #size-cells = <0>;
461 #power-domain-cells = <0>;
468 #power-domain-cells = <0>;
474 #power-domain-cells = <0>;
480 #power-domain-cells = <0>;
488 #power-domain-cells = <0>;
492 #power-domain-cells = <0>;
496 #power-domain-cells = <0>;
503 #size-cells = <0>;
509 #size-cells = <0>;
514 #power-domain-cells = <0>;
525 reg = <0 0x10007000 0 0x100>;
531 reg = <0 0x10008000 0 0x1000>;
539 reg = <0 0x1000d000 0 0x1000>;
550 reg = <0 0x10013000 0 0xbc>;
558 reg = <0 0x10020000 0 0x30000>,
559 <0 0x10050000 0 0x100>;
573 reg = <0 0x10200620 0 0x20>;
578 reg = <0 0x10205000 0 0x1000>;
590 reg = <0 0x10206000 0 0x1000>;
594 reg = <0x528 0xc>;
600 reg = <0 0x10209000 0 0x1000>;
606 reg = <0 0x10209100 0 0x24>;
610 mediatek,ibias = <0xa>;
611 mediatek,ibias_up = <0x1c>;
612 #clock-cells = <0>;
613 #phy-cells = <0>;
619 reg = <0 0x10212000 0 0x1000>;
628 reg = <0 0x10215000 0 0x1000>;
631 #clock-cells = <0>;
632 #phy-cells = <0>;
638 reg = <0 0x10216000 0 0x1000>;
641 #clock-cells = <0>;
642 #phy-cells = <0>;
651 reg = <0 0x10221000 0 0x1000>,
652 <0 0x10222000 0 0x2000>,
653 <0 0x10224000 0 0x2000>,
654 <0 0x10226000 0 0x2000>;
661 reg = <0 0x11001000 0 0x1000>;
670 reg = <0 0x11002000 0 0x400>;
680 reg = <0 0x11003000 0 0x400>;
690 reg = <0 0x11004000 0 0x400>;
700 reg = <0 0x11005000 0 0x400>;
709 reg = <0 0x11007000 0 0x70>,
710 <0 0x11000100 0 0x80>;
717 pinctrl-0 = <&i2c0_pins_a>;
719 #size-cells = <0>;
725 reg = <0 0x11008000 0 0x70>,
726 <0 0x11000180 0 0x80>;
733 pinctrl-0 = <&i2c1_pins_a>;
735 #size-cells = <0>;
741 reg = <0 0x11009000 0 0x70>,
742 <0 0x11000200 0 0x80>;
749 pinctrl-0 = <&i2c2_pins_a>;
751 #size-cells = <0>;
758 #size-cells = <0>;
759 reg = <0 0x1100a000 0 0x1000>;
769 #thermal-sensor-cells = <0>;
771 reg = <0 0x1100b000 0 0x1000>;
772 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
784 reg = <0 0x1100d000 0 0xe0>;
792 #size-cells = <0>;
798 reg = <0 0x11010000 0 0x70>,
799 <0 0x11000280 0 0x80>;
806 pinctrl-0 = <&i2c3_pins_a>;
808 #size-cells = <0>;
814 reg = <0 0x11011000 0 0x70>,
815 <0 0x11000300 0 0x80>;
822 pinctrl-0 = <&i2c4_pins_a>;
824 #size-cells = <0>;
831 reg = <0 0x11012000 0 0x1C>;
838 reg = <0 0x11013000 0 0x70>,
839 <0 0x11000080 0 0x80>;
846 pinctrl-0 = <&i2c6_pins_a>;
848 #size-cells = <0>;
854 reg = <0 0x11220000 0 0x1000>;
885 reg = <0 0x11230000 0 0x1000>;
895 reg = <0 0x11240000 0 0x1000>;
905 reg = <0 0x11250000 0 0x1000>;
915 reg = <0 0x11260000 0 0x1000>;
925 reg = <0 0x11271000 0 0x3000>,
926 <0 0x11280700 0 0x0100>;
935 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
944 reg = <0 0x11270000 0 0x1000>;
956 reg = <0 0x11290000 0 0x800>;
963 reg = <0 0x11290800 0 0x100>;
971 reg = <0 0x11290900 0 0x700>;
979 reg = <0 0x11291000 0 0x100>;
989 reg = <0 0x14000000 0 0x1000>;
995 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
997 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1003 reg = <0 0x14001000 0 0x1000>;
1013 reg = <0 0x14002000 0 0x1000>;
1022 reg = <0 0x14003000 0 0x1000>;
1029 reg = <0 0x14004000 0 0x1000>;
1036 reg = <0 0x14005000 0 0x1000>;
1043 reg = <0 0x14006000 0 0x1000>;
1051 reg = <0 0x14007000 0 0x1000>;
1059 reg = <0 0x14008000 0 0x1000>;
1067 reg = <0 0x1400c000 0 0x1000>;
1072 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1077 reg = <0 0x1400d000 0 0x1000>;
1082 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1087 reg = <0 0x1400e000 0 0x1000>;
1092 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1097 reg = <0 0x1400f000 0 0x1000>;
1102 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1107 reg = <0 0x14010000 0 0x1000>;
1112 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1117 reg = <0 0x14011000 0 0x1000>;
1122 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1127 reg = <0 0x14012000 0 0x1000>;
1132 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1137 reg = <0 0x14013000 0 0x1000>;
1141 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1146 reg = <0 0x14014000 0 0x1000>;
1150 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1155 reg = <0 0x14015000 0 0x1000>;
1159 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1164 reg = <0 0x14016000 0 0x1000>;
1168 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1173 reg = <0 0x14017000 0 0x1000>;
1180 reg = <0 0x14018000 0 0x1000>;
1187 reg = <0 0x14019000 0 0x1000>;
1194 reg = <0 0x1401a000 0 0x1000>;
1198 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
1203 reg = <0 0x1401b000 0 0x1000>;
1218 reg = <0 0x1401c000 0 0x1000>;
1232 reg = <0 0x1401d000 0 0x1000>;
1251 reg = <0 0x1401e000 0 0x1000>;
1262 reg = <0 0x1401f000 0 0x1000>;
1272 reg = <0 0x14020000 0 0x1000>;
1276 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
1283 reg = <0 0x14021000 0 0x1000>;
1293 reg = <0 0x14022000 0 0x1000>;
1302 reg = <0 0x14023000 0 0x1000>;
1304 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
1309 reg = <0 0x14025000 0 0x400>;
1317 pinctrl-0 = <&hdmi_pin>;
1320 mediatek,syscon-hdmi = <&mmsys 0x900>;
1327 #size-cells = <0>;
1329 port@0 {
1330 reg = <0>;
1341 reg = <0 0x14027000 0 0x1000>;
1351 reg = <0 0x15000000 0 0x1000>;
1357 reg = <0 0x15001000 0 0x1000>;
1367 reg = <0 0x16000000 0 0x1000>;
1373 reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */
1374 <0 0x16021000 0 0x800>, /* VDEC_LD */
1375 <0 0x16021800 0 0x800>, /* VDEC_TOP */
1376 <0 0x16022000 0 0x1000>, /* VDEC_CM */
1377 <0 0x16023000 0 0x1000>, /* VDEC_AD */
1378 <0 0x16024000 0 0x1000>, /* VDEC_AV */
1379 <0 0x16025000 0 0x1000>, /* VDEC_PP */
1380 <0 0x16026800 0 0x800>, /* VDEC_HWD */
1381 <0 0x16027000 0 0x800>, /* VDEC_HWQ */
1382 <0 0x16027800 0 0x800>, /* VDEC_HWB */
1383 <0 0x16028400 0 0x400>; /* VDEC_HWG */
1422 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1427 reg = <0 0x16010000 0 0x1000>;
1437 reg = <0 0x18000000 0 0x1000>;
1443 reg = <0 0x18001000 0 0x1000>;
1453 reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
1476 reg = <0 0x18004000 0 0x1000>;
1489 reg = <0 0x19000000 0 0x1000>;
1495 reg = <0 0x19001000 0 0x1000>;
1505 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */