Lines Matching +full:spi +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
6 #include <dt-bindings/pinctrl/mt65xx.h>
7 #include <dt-bindings/reset/mediatek,mt7988-resets.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 compatible = "mediatek,mt7988-cci", "mediatek,mt8183-cci";
19 clock-names = "cci", "intermediate";
20 operating-points-v2 = <&cci_opp>;
23 cci_opp: opp-table-cci {
24 compatible = "operating-points-v2";
25 opp-shared;
26 opp-480000000 {
27 opp-hz = /bits/ 64 <480000000>;
28 opp-microvolt = <850000>;
30 opp-660000000 {
31 opp-hz = /bits/ 64 <660000000>;
32 opp-microvolt = <850000>;
34 opp-900000000 {
35 opp-hz = /bits/ 64 <900000000>;
36 opp-microvolt = <850000>;
38 opp-1080000000 {
39 opp-hz = /bits/ 64 <1080000000>;
40 opp-microvolt = <900000>;
45 #address-cells = <1>;
46 #size-cells = <0>;
49 compatible = "arm,cortex-a73";
52 enable-method = "psci";
55 clock-names = "cpu", "intermediate";
56 operating-points-v2 = <&cluster0_opp>;
61 compatible = "arm,cortex-a73";
64 enable-method = "psci";
67 clock-names = "cpu", "intermediate";
68 operating-points-v2 = <&cluster0_opp>;
73 compatible = "arm,cortex-a73";
76 enable-method = "psci";
79 clock-names = "cpu", "intermediate";
80 operating-points-v2 = <&cluster0_opp>;
85 compatible = "arm,cortex-a73";
88 enable-method = "psci";
91 clock-names = "cpu", "intermediate";
92 operating-points-v2 = <&cluster0_opp>;
96 cluster0_opp: opp-table-0 {
97 compatible = "operating-points-v2";
98 opp-shared;
100 opp-800000000 {
101 opp-hz = /bits/ 64 <800000000>;
102 opp-microvolt = <850000>;
104 opp-1100000000 {
105 opp-hz = /bits/ 64 <1100000000>;
106 opp-microvolt = <850000>;
108 opp-1500000000 {
109 opp-hz = /bits/ 64 <1500000000>;
110 opp-microvolt = <850000>;
112 opp-1800000000 {
113 opp-hz = /bits/ 64 <1800000000>;
114 opp-microvolt = <900000>;
119 oscillator-40m {
120 compatible = "fixed-clock";
121 clock-frequency = <40000000>;
122 #clock-cells = <0>;
123 clock-output-names = "clkxtal";
127 compatible = "arm,cortex-a73-pmu";
128 interrupt-parent = <&gic>;
133 compatible = "arm,psci-0.2";
137 reserved-memory {
138 #address-cells = <2>;
139 #size-cells = <2>;
145 no-map;
150 compatible = "simple-bus";
152 #address-cells = <2>;
153 #size-cells = <2>;
155 gic: interrupt-controller@c000000 {
156 compatible = "arm,gic-v3";
162 interrupt-parent = <&gic>;
164 interrupt-controller;
165 #interrupt-cells = <3>;
168 infracfg: clock-controller@10001000 {
169 compatible = "mediatek,mt7988-infracfg", "syscon";
171 #clock-cells = <1>;
172 #reset-cells = <1>;
175 topckgen: clock-controller@1001b000 {
176 compatible = "mediatek,mt7988-topckgen", "syscon";
178 #clock-cells = <1>;
182 compatible = "mediatek,mt7988-wdt";
185 #reset-cells = <1>;
188 apmixedsys: clock-controller@1001e000 {
189 compatible = "mediatek,mt7988-apmixedsys";
191 #clock-cells = <1>;
195 compatible = "mediatek,mt7988-pinctrl";
203 reg-names = "gpio", "iocfg_tr",
206 gpio-controller;
207 #gpio-cells = <2>;
208 gpio-ranges = <&pio 0 0 84>;
209 interrupt-controller;
211 interrupt-parent = <&gic>;
212 #interrupt-cells = <2>;
214 pcie0_pins: pcie0-pins {
222 pcie1_pins: pcie1-pins {
230 pcie2_pins: pcie2-pins {
238 pcie3_pins: pcie3-pins {
246 spi1_pins: spi1-pins {
248 function = "spi";
253 uart0_pins: uart0-pins {
262 compatible = "mediatek,mt7988-pwm";
274 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
276 #pwm-cells = <2>;
281 compatible = "mediatek,mt7988-mcusys", "syscon";
283 #clock-cells = <1>;
287 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
290 interrupt-names = "uart", "wakeup";
293 clock-names = "baud", "bus";
294 pinctrl-names = "default";
295 pinctrl-0 = <&uart0_pins>;
300 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
303 interrupt-names = "uart", "wakeup";
306 clock-names = "baud", "bus";
311 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
314 interrupt-names = "uart", "wakeup";
317 clock-names = "baud", "bus";
322 compatible = "mediatek,mt7981-i2c";
326 clock-div = <1>;
329 clock-names = "main", "dma";
330 #address-cells = <1>;
331 #size-cells = <0>;
336 compatible = "mediatek,mt7981-i2c";
340 clock-div = <1>;
343 clock-names = "main", "dma";
344 #address-cells = <1>;
345 #size-cells = <0>;
350 compatible = "mediatek,mt7981-i2c";
354 clock-div = <1>;
357 clock-names = "main", "dma";
358 #address-cells = <1>;
359 #size-cells = <0>;
363 spi0: spi@11007000 {
364 compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";
371 clock-names = "parent-clk", "sel-clk", "spi-clk",
373 #address-cells = <1>;
374 #size-cells = <0>;
378 spi1: spi@11008000 {
379 compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm";
386 clock-names = "parent-clk", "sel-clk", "spi-clk",
388 #address-cells = <1>;
389 #size-cells = <0>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&spi1_pins>;
395 spi2: spi@11009000 {
396 compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";
403 clock-names = "parent-clk", "sel-clk", "spi-clk",
405 #address-cells = <1>;
406 #size-cells = <0>;
411 compatible = "mediatek,mt7988-lvts-ap";
412 #thermal-sensor-cells = <1>;
417 nvmem-cells = <&lvts_calibration>;
418 nvmem-cell-names = "lvts-calib-data-1";
422 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
425 reg-names = "mac", "ippc";
432 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
439 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
442 reg-names = "mac", "ippc";
449 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
456 compatible = "mediatek,mt7988-mmc";
464 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
466 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
468 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
469 #address-cells = <1>;
470 #size-cells = <0>;
475 compatible = "mediatek,mt7986-pcie",
476 "mediatek,mt8192-pcie";
478 #address-cells = <3>;
479 #size-cells = <2>;
481 reg-names = "pcie-mac";
482 linux,pci-domain = <3>;
484 bus-range = <0x00 0xff>;
493 clock-names = "pl_250m", "tl_26m", "peri_26m",
495 pinctrl-names = "default";
496 pinctrl-0 = <&pcie2_pins>;
500 phy-names = "pcie-phy";
502 #interrupt-cells = <1>;
503 interrupt-map-mask = <0 0 0 0x7>;
504 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
508 pcie_intc2: interrupt-controller {
509 #address-cells = <0>;
510 #interrupt-cells = <1>;
511 interrupt-controller;
516 compatible = "mediatek,mt7986-pcie",
517 "mediatek,mt8192-pcie";
519 #address-cells = <3>;
520 #size-cells = <2>;
522 reg-names = "pcie-mac";
523 linux,pci-domain = <2>;
525 bus-range = <0x00 0xff>;
534 clock-names = "pl_250m", "tl_26m", "peri_26m",
536 pinctrl-names = "default";
537 pinctrl-0 = <&pcie3_pins>;
540 #interrupt-cells = <1>;
541 interrupt-map-mask = <0 0 0 0x7>;
542 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
546 pcie_intc3: interrupt-controller {
547 #address-cells = <0>;
548 #interrupt-cells = <1>;
549 interrupt-controller;
554 compatible = "mediatek,mt7986-pcie",
555 "mediatek,mt8192-pcie";
557 #address-cells = <3>;
558 #size-cells = <2>;
560 reg-names = "pcie-mac";
561 linux,pci-domain = <0>;
563 bus-range = <0x00 0xff>;
572 clock-names = "pl_250m", "tl_26m", "peri_26m",
574 pinctrl-names = "default";
575 pinctrl-0 = <&pcie0_pins>;
578 #interrupt-cells = <1>;
579 interrupt-map-mask = <0 0 0 0x7>;
580 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
584 pcie_intc0: interrupt-controller {
585 #address-cells = <0>;
586 #interrupt-cells = <1>;
587 interrupt-controller;
592 compatible = "mediatek,mt7986-pcie",
593 "mediatek,mt8192-pcie";
595 #address-cells = <3>;
596 #size-cells = <2>;
598 reg-names = "pcie-mac";
599 linux,pci-domain = <1>;
601 bus-range = <0x00 0xff>;
610 clock-names = "pl_250m", "tl_26m", "peri_26m",
612 pinctrl-names = "default";
613 pinctrl-0 = <&pcie1_pins>;
616 #interrupt-cells = <1>;
617 interrupt-map-mask = <0 0 0 0x7>;
618 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
622 pcie_intc1: interrupt-controller {
623 #address-cells = <0>;
624 #interrupt-cells = <1>;
625 interrupt-controller;
629 tphy: t-phy@11c50000 {
630 compatible = "mediatek,mt7986-tphy",
631 "mediatek,generic-tphy-v2";
632 #address-cells = <2>;
633 #size-cells = <2>;
637 tphyu2port0: usb-phy@11c50000 {
640 clock-names = "ref";
641 #phy-cells = <1>;
644 tphyu3port0: usb-phy@11c50700 {
647 clock-names = "ref";
648 #phy-cells = <1>;
653 topmisc: system-controller@11d10084 {
654 compatible = "mediatek,mt7988-topmisc",
659 xsphy: xs-phy@11e10000 {
660 compatible = "mediatek,mt7988-xsphy",
662 #address-cells = <2>;
663 #size-cells = <2>;
667 xphyu2port0: usb-phy@11e10000 {
670 clock-names = "ref";
671 #phy-cells = <1>;
674 xphyu3port0: usb-phy@11e13000 {
677 clock-names = "ref";
678 #phy-cells = <1>;
679 mediatek,syscon-type = <&topmisc 0x194 0>;
683 clock-controller@11f40000 {
684 compatible = "mediatek,mt7988-xfi-pll";
687 #clock-cells = <1>;
691 compatible = "mediatek,mt7988-efuse", "mediatek,efuse";
693 #address-cells = <1>;
694 #size-cells = <1>;
717 clock-controller@15000000 {
718 compatible = "mediatek,mt7988-ethsys", "syscon";
720 #clock-cells = <1>;
721 #reset-cells = <1>;
724 clock-controller@15031000 {
725 compatible = "mediatek,mt7988-ethwarp";
727 #clock-cells = <1>;
728 #reset-cells = <1>;
732 thermal-zones {
733 cpu_thermal: cpu-thermal {
734 polling-delay-passive = <1000>;
735 polling-delay = <1000>;
736 thermal-sensors = <&lvts 0>;
748 compatible = "arm,armv8-timer";
749 interrupt-parent = <&gic>;