Lines Matching +full:mt7986 +full:- +full:wed
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mt7986-clk.h>
10 #include <dt-bindings/reset/mt7986-resets.h>
11 #include <dt-bindings/phy/phy.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
19 clk40m: oscillator-40m {
20 compatible = "fixed-clock";
21 clock-frequency = <40000000>;
22 #clock-cells = <0>;
23 clock-output-names = "clkxtal";
27 #address-cells = <1>;
28 #size-cells = <0>;
31 compatible = "arm,cortex-a53";
32 enable-method = "psci";
34 #cooling-cells = <2>;
39 compatible = "arm,cortex-a53";
40 enable-method = "psci";
42 #cooling-cells = <2>;
47 compatible = "arm,cortex-a53";
48 enable-method = "psci";
50 #cooling-cells = <2>;
55 enable-method = "psci";
56 compatible = "arm,cortex-a53";
58 #cooling-cells = <2>;
63 compatible = "arm,psci-0.2";
67 reserved-memory {
68 #address-cells = <2>;
69 #size-cells = <2>;
74 no-map;
77 wmcpu_emi: wmcpu-reserved@4fc00000 {
78 no-map;
82 wo_emi0: wo-emi@4fd00000 {
84 no-map;
87 wo_emi1: wo-emi@4fd40000 {
89 no-map;
92 wo_ilm0: wo-ilm@151e0000 {
94 no-map;
97 wo_ilm1: wo-ilm@151f0000 {
99 no-map;
102 wo_data: wo-data@4fd80000 {
104 no-map;
107 wo_dlm0: wo-dlm@151e8000 {
109 no-map;
112 wo_dlm1: wo-dlm@151f8000 {
114 no-map;
117 wo_boot: wo-boot@15194000 {
119 no-map;
125 compatible = "arm,armv8-timer";
126 interrupt-parent = <&gic>;
134 #address-cells = <2>;
135 #size-cells = <2>;
136 compatible = "simple-bus";
139 gic: interrupt-controller@c000000 {
140 compatible = "arm,gic-v3";
141 #interrupt-cells = <3>;
142 interrupt-parent = <&gic>;
143 interrupt-controller;
153 compatible = "mediatek,mt7986-infracfg", "syscon";
155 #clock-cells = <1>;
158 wed_pcie: wed-pcie@10003000 {
159 compatible = "mediatek,mt7986-wed-pcie",
165 compatible = "mediatek,mt7986-topckgen", "syscon";
167 #clock-cells = <1>;
171 compatible = "mediatek,mt7986-wdt";
174 #reset-cells = <1>;
179 compatible = "mediatek,mt7986-apmixedsys";
181 #clock-cells = <1>;
185 compatible = "mediatek,mt7986a-pinctrl";
194 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
196 gpio-controller;
197 #gpio-cells = <2>;
198 gpio-ranges = <&pio 0 0 100>;
199 interrupt-controller;
201 interrupt-parent = <&gic>;
202 #interrupt-cells = <2>;
206 compatible = "mediatek,mt7986-sgmiisys_0",
209 #clock-cells = <1>;
213 compatible = "mediatek,mt7986-sgmiisys_1",
216 #clock-cells = <1>;
220 compatible = "mediatek,mt7986-rng",
221 "mediatek,mt7623-rng";
224 clock-names = "rng";
229 compatible = "inside-secure,safexcel-eip97";
235 interrupt-names = "ring0", "ring1", "ring2", "ring3";
237 clock-names = "infra_eip97_ck";
238 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
239 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
244 compatible = "mediatek,mt7986-pwm";
246 #clock-cells = <1>;
247 #pwm-cells = <2>;
253 clock-names = "top", "main", "pwm1", "pwm2";
258 compatible = "mediatek,mt7986-uart",
259 "mediatek,mt6577-uart";
264 clock-names = "baud", "bus";
265 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
267 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
273 compatible = "mediatek,mt7986-uart",
274 "mediatek,mt6577-uart";
279 clock-names = "baud", "bus";
280 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
281 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
286 compatible = "mediatek,mt7986-uart",
287 "mediatek,mt6577-uart";
292 clock-names = "baud", "bus";
293 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
294 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
299 compatible = "mediatek,mt7986-i2c";
303 clock-div = <5>;
306 clock-names = "main", "dma";
307 #address-cells = <1>;
308 #size-cells = <0>;
313 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
314 #address-cells = <1>;
315 #size-cells = <0>;
322 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
327 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
328 #address-cells = <1>;
329 #size-cells = <0>;
336 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
341 compatible = "mediatek,mt7986-auxadc";
344 clock-names = "main";
345 #io-channel-cells = <1>;
350 compatible = "mediatek,mt7986-xhci",
351 "mediatek,mtk-xhci";
354 reg-names = "mac", "ippc";
361 clock-names = "sys_ck",
373 compatible = "mediatek,mt7986-mmc";
377 assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
379 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
386 clock-names = "source", "hclk", "source_cg", "bus_clk",
392 #thermal-sensor-cells = <1>;
393 compatible = "mediatek,mt7986-thermal";
399 clock-names = "therm", "auxadc", "adc_32k";
402 nvmem-cells = <&thermal_calibration>;
403 nvmem-cell-names = "calibration-data";
407 compatible = "mediatek,mt7986-pcie",
408 "mediatek,mt8192-pcie";
410 #address-cells = <3>;
411 #size-cells = <2>;
413 reg-names = "pcie-mac";
415 bus-range = <0x00 0xff>;
422 clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
426 phy-names = "pcie-phy";
428 #interrupt-cells = <1>;
429 interrupt-map-mask = <0 0 0 0x7>;
430 interrupt-map = <0 0 0 1 &pcie_intc 0>,
434 pcie_intc: interrupt-controller {
435 #address-cells = <0>;
436 #interrupt-cells = <1>;
437 interrupt-controller;
441 pcie_phy: t-phy {
442 compatible = "mediatek,mt7986-tphy",
443 "mediatek,generic-tphy-v2";
444 #address-cells = <2>;
445 #size-cells = <2>;
449 pcie_port: pcie-phy@11c00000 {
452 clock-names = "ref";
453 #phy-cells = <1>;
458 compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
460 #address-cells = <1>;
461 #size-cells = <1>;
468 usb_phy: t-phy@11e10000 {
469 compatible = "mediatek,mt7986-tphy",
470 "mediatek,generic-tphy-v2";
471 #address-cells = <1>;
472 #size-cells = <1>;
476 u2port0: usb-phy@0 {
480 clock-names = "ref", "da_ref";
481 #phy-cells = <1>;
484 u3port0: usb-phy@700 {
487 clock-names = "ref";
488 #phy-cells = <1>;
491 u2port1: usb-phy@1000 {
495 clock-names = "ref", "da_ref";
496 #phy-cells = <1>;
501 #address-cells = <1>;
502 #size-cells = <1>;
503 compatible = "mediatek,mt7986-ethsys",
506 #clock-cells = <1>;
507 #reset-cells = <1>;
510 wed0: wed@15010000 {
511 compatible = "mediatek,mt7986-wed",
514 interrupt-parent = <&gic>;
516 memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
518 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
519 "wo-data", "wo-boot";
520 mediatek,wo-ccif = <&wo_ccif0>;
523 wed1: wed@15011000 {
524 compatible = "mediatek,mt7986-wed",
527 interrupt-parent = <&gic>;
529 memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
531 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
532 "wo-data", "wo-boot";
533 mediatek,wo-ccif = <&wo_ccif1>;
537 compatible = "mediatek,mt7986-wo-ccif", "syscon";
539 interrupt-parent = <&gic>;
544 compatible = "mediatek,mt7986-wo-ccif", "syscon";
546 interrupt-parent = <&gic>;
551 compatible = "mediatek,mt7986-eth";
572 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
578 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
580 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
584 mediatek,wed-pcie = <&wed_pcie>;
585 mediatek,wed = <&wed0>, <&wed1>;
586 #reset-cells = <1>;
587 #address-cells = <1>;
588 #size-cells = <0>;
593 compatible = "mediatek,mt7986-wmac";
595 reset-names = "consys";
598 clock-names = "mcu", "ap2conn";
606 memory-region = <&wmcpu_emi>;
610 thermal-zones {
611 cpu_thermal: cpu-thermal {
612 polling-delay-passive = <1000>;
613 polling-delay = <1000>;
614 thermal-sensors = <&thermal 0>;
629 cpu_trip_active_high: active-high {
635 cpu_trip_active_med: active-med {
641 cpu_trip_active_low: active-low {