Lines Matching +full:opp +full:- +full:1300000000
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
23 cpu_opp_table: opp-table {
24 compatible = "operating-points-v2";
25 opp-shared;
26 opp-300000000 {
27 opp-hz = /bits/ 64 <30000000>;
28 opp-microvolt = <950000>;
31 opp-437500000 {
32 opp-hz = /bits/ 64 <437500000>;
33 opp-microvolt = <1000000>;
36 opp-600000000 {
37 opp-hz = /bits/ 64 <600000000>;
38 opp-microvolt = <1050000>;
41 opp-812500000 {
42 opp-hz = /bits/ 64 <812500000>;
43 opp-microvolt = <1100000>;
46 opp-1025000000 {
47 opp-hz = /bits/ 64 <1025000000>;
48 opp-microvolt = <1150000>;
51 opp-1137500000 {
52 opp-hz = /bits/ 64 <1137500000>;
53 opp-microvolt = <1200000>;
56 opp-1262500000 {
57 opp-hz = /bits/ 64 <1262500000>;
58 opp-microvolt = <1250000>;
61 opp-1350000000 {
62 opp-hz = /bits/ 64 <1350000000>;
63 opp-microvolt = <1310000>;
68 #address-cells = <2>;
69 #size-cells = <0>;
73 compatible = "arm,cortex-a53";
77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = <&cpu_opp_table>;
79 #cooling-cells = <2>;
80 enable-method = "psci";
81 clock-frequency = <1300000000>;
82 cci-control-port = <&cci_control2>;
83 next-level-cache = <&L2>;
88 compatible = "arm,cortex-a53";
92 clock-names = "cpu", "intermediate";
93 operating-points-v2 = <&cpu_opp_table>;
94 #cooling-cells = <2>;
95 enable-method = "psci";
96 clock-frequency = <1300000000>;
97 cci-control-port = <&cci_control2>;
98 next-level-cache = <&L2>;
101 L2: l2-cache {
103 cache-level = <2>;
104 cache-unified;
109 compatible = "fixed-clock";
110 clock-frequency = <40000000>;
111 #clock-cells = <0>;
115 compatible = "fixed-clock";
116 #clock-cells = <0>;
117 clock-frequency = <25000000>;
118 clock-output-names = "clkxtal";
122 compatible = "arm,psci-0.2";
127 compatible = "arm,cortex-a53-pmu";
130 interrupt-affinity = <&cpu0>, <&cpu1>;
133 reserved-memory {
134 #address-cells = <2>;
135 #size-cells = <2>;
141 no-map;
145 thermal-zones {
146 cpu_thermal: cpu-thermal {
147 polling-delay-passive = <1000>;
148 polling-delay = <1000>;
150 thermal-sensors = <&thermal 0>;
153 cpu_passive: cpu-passive {
159 cpu_active: cpu-active {
165 cpu_hot: cpu-hot {
171 cpu-crit {
178 cooling-maps {
181 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
187 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
193 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
201 compatible = "arm,armv8-timer";
202 interrupt-parent = <&gic>;
214 compatible = "mediatek,mt7622-infracfg",
217 #clock-cells = <1>;
218 #reset-cells = <1>;
222 compatible = "mediatek,mt7622-pwrap";
224 reg-names = "pwrap";
226 clock-names = "spi", "wrap";
228 reset-names = "pwrap";
234 compatible = "mediatek,mt7622-pericfg",
237 #clock-cells = <1>;
238 #reset-cells = <1>;
241 scpsys: power-controller@10006000 {
242 compatible = "mediatek,mt7622-scpsys",
244 #power-domain-cells = <1>;
252 clock-names = "hif_sel";
256 compatible = "mediatek,mt7622-cir";
261 clock-names = "clk", "bus";
265 sysirq: interrupt-controller@10200620 {
266 compatible = "mediatek,mt7622-sysirq",
267 "mediatek,mt6577-sysirq";
268 interrupt-controller;
269 #interrupt-cells = <3>;
270 interrupt-parent = <&gic>;
275 compatible = "mediatek,mt7622-efuse",
278 #address-cells = <1>;
279 #size-cells = <1>;
287 compatible = "mediatek,mt7622-apmixedsys",
290 #clock-cells = <1>;
294 compatible = "mediatek,mt7622-topckgen",
297 #clock-cells = <1>;
301 compatible = "mediatek,mt7622-rng",
302 "mediatek,mt7623-rng";
305 clock-names = "rng";
309 compatible = "mediatek,mt7622-pinctrl";
312 reg-names = "base", "eint";
313 gpio-controller;
314 #gpio-cells = <2>;
315 gpio-ranges = <&pio 0 0 103>;
316 interrupt-controller;
318 interrupt-parent = <&gic>;
319 #interrupt-cells = <2>;
323 compatible = "mediatek,mt7622-wdt",
324 "mediatek,mt6589-wdt";
329 compatible = "mediatek,mt7622-rtc",
330 "mediatek,soc-rtc";
334 clock-names = "rtc";
337 gic: interrupt-controller@10300000 {
338 compatible = "arm,gic-400";
339 interrupt-controller;
340 #interrupt-cells = <3>;
341 interrupt-parent = <&gic>;
349 compatible = "arm,cci-400";
350 #address-cells = <1>;
351 #size-cells = <1>;
355 cci_control0: slave-if@1000 {
356 compatible = "arm,cci-400-ctrl-if";
357 interface-type = "ace-lite";
361 cci_control1: slave-if@4000 {
362 compatible = "arm,cci-400-ctrl-if";
363 interface-type = "ace";
367 cci_control2: slave-if@5000 {
368 compatible = "arm,cci-400-ctrl-if", "syscon";
369 interface-type = "ace";
374 compatible = "arm,cci-400-pmu,r1";
385 compatible = "mediatek,mt7622-auxadc";
388 clock-names = "main";
389 #io-channel-cells = <1>;
393 compatible = "mediatek,mt7622-uart",
394 "mediatek,mt6577-uart";
399 clock-names = "baud", "bus";
404 compatible = "mediatek,mt7622-uart",
405 "mediatek,mt6577-uart";
410 clock-names = "baud", "bus";
415 compatible = "mediatek,mt7622-uart",
416 "mediatek,mt6577-uart";
421 clock-names = "baud", "bus";
426 compatible = "mediatek,mt7622-uart",
427 "mediatek,mt6577-uart";
432 clock-names = "baud", "bus";
437 compatible = "mediatek,mt7622-pwm";
439 #pwm-cells = <2>;
449 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
455 compatible = "mediatek,mt7622-i2c";
459 clock-div = <16>;
462 clock-names = "main", "dma";
463 #address-cells = <1>;
464 #size-cells = <0>;
469 compatible = "mediatek,mt7622-i2c";
473 clock-div = <16>;
476 clock-names = "main", "dma";
477 #address-cells = <1>;
478 #size-cells = <0>;
483 compatible = "mediatek,mt7622-i2c";
487 clock-div = <16>;
490 clock-names = "main", "dma";
491 #address-cells = <1>;
492 #size-cells = <0>;
497 compatible = "mediatek,mt7622-spi";
503 clock-names = "parent-clk", "sel-clk", "spi-clk";
504 #address-cells = <1>;
505 #size-cells = <0>;
510 #thermal-sensor-cells = <1>;
511 compatible = "mediatek,mt7622-thermal";
516 clock-names = "therm", "auxadc";
518 reset-names = "therm";
521 nvmem-cells = <&thermal_calibration>;
522 nvmem-cell-names = "calibration-data";
526 compatible = "mediatek,mt7622-btif",
527 "mediatek,mtk-btif";
531 reg-shift = <2>;
532 reg-io-width = <4>;
536 compatible = "mediatek,mt7622-bluetooth";
537 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
539 clock-names = "ref";
543 nandc: nand-controller@1100d000 {
544 compatible = "mediatek,mt7622-nfc";
549 clock-names = "nfi_clk", "pad_clk";
550 ecc-engine = <&bch>;
551 #address-cells = <1>;
552 #size-cells = <0>;
557 compatible = "mediatek,mt7622-snand";
561 clock-names = "nfi_clk", "pad_clk";
562 nand-ecc-engine = <&bch>;
563 #address-cells = <1>;
564 #size-cells = <0>;
569 compatible = "mediatek,mt7622-ecc";
573 clock-names = "nfiecc_clk";
578 compatible = "mediatek,mt7622-nor",
579 "mediatek,mt8173-nor";
583 clock-names = "spi", "sf";
584 #address-cells = <1>;
585 #size-cells = <0>;
590 compatible = "mediatek,mt7622-spi";
596 clock-names = "parent-clk", "sel-clk", "spi-clk";
597 #address-cells = <1>;
598 #size-cells = <0>;
603 compatible = "mediatek,mt7622-uart",
604 "mediatek,mt6577-uart";
609 clock-names = "baud", "bus";
613 audsys: clock-controller@11220000 {
614 compatible = "mediatek,mt7622-audsys", "syscon";
616 #clock-cells = <1>;
618 afe: audio-controller {
619 compatible = "mediatek,mt7622-audio";
622 interrupt-names = "afe", "asys";
658 clock-names = "infra_sys_audio_clk",
692 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
696 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
698 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
703 compatible = "mediatek,mt7622-mmc";
708 clock-names = "source", "hclk";
710 reset-names = "hrst";
715 compatible = "mediatek,mt7622-mmc";
720 clock-names = "source", "hclk";
722 reset-names = "hrst";
727 compatible = "mediatek,mt7622-wmac";
734 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
738 compatible = "mediatek,mt7622-ssusbsys",
741 #clock-cells = <1>;
742 #reset-cells = <1>;
746 compatible = "mediatek,mt7622-xhci",
747 "mediatek,mtk-xhci";
750 reg-names = "mac", "ippc";
752 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
757 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
765 u3phy: t-phy@1a0c4000 {
766 compatible = "mediatek,mt7622-tphy",
767 "mediatek,generic-tphy-v1";
769 #address-cells = <2>;
770 #size-cells = <2>;
774 u2port0: usb-phy@1a0c4800 {
776 #phy-cells = <1>;
778 clock-names = "ref";
781 u3port0: usb-phy@1a0c4900 {
783 #phy-cells = <1>;
785 clock-names = "ref";
788 u2port1: usb-phy@1a0c5000 {
790 #phy-cells = <1>;
792 clock-names = "ref";
797 compatible = "mediatek,mt7622-pciesys",
800 #clock-cells = <1>;
801 #reset-cells = <1>;
805 compatible = "mediatek,generic-pciecfg", "syscon";
810 compatible = "mediatek,mt7622-pcie";
813 reg-names = "port0";
814 linux,pci-domain = <0>;
815 #address-cells = <3>;
816 #size-cells = <2>;
818 interrupt-names = "pcie_irq";
825 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
828 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
829 bus-range = <0x00 0xff>;
833 #interrupt-cells = <1>;
834 interrupt-map-mask = <0 0 0 7>;
835 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
839 pcie_intc0: interrupt-controller {
840 interrupt-controller;
841 #address-cells = <0>;
842 #interrupt-cells = <1>;
847 compatible = "mediatek,mt7622-pcie";
850 reg-names = "port1";
851 linux,pci-domain = <1>;
852 #address-cells = <3>;
853 #size-cells = <2>;
855 interrupt-names = "pcie_irq";
863 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
866 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
867 bus-range = <0x00 0xff>;
871 #interrupt-cells = <1>;
872 interrupt-map-mask = <0 0 0 7>;
873 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
877 pcie_intc1: interrupt-controller {
878 interrupt-controller;
879 #address-cells = <0>;
880 #interrupt-cells = <1>;
885 compatible = "mediatek,mt7622-ahci",
886 "mediatek,mtk-ahci";
889 interrupt-names = "hostc";
895 clock-names = "ahb", "axi", "asic", "rbc", "pm";
897 phy-names = "sata-phy";
898 ports-implemented = <0x1>;
899 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
903 reset-names = "axi", "sw", "reg";
904 mediatek,phy-mode = <&pciesys>;
908 sata_phy: t-phy {
909 compatible = "mediatek,mt7622-tphy",
910 "mediatek,generic-tphy-v1";
911 #address-cells = <2>;
912 #size-cells = <2>;
916 sata_port: sata-phy@1a243000 {
919 clock-names = "ref";
920 #phy-cells = <1>;
925 compatible = "mediatek,mt7622-hifsys", "syscon";
930 compatible = "mediatek,mt7622-ethsys",
933 #clock-cells = <1>;
934 #reset-cells = <1>;
937 hsdma: dma-controller@1b007000 {
938 compatible = "mediatek,mt7622-hsdma";
942 clock-names = "hsdma";
943 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
944 #dma-cells = <1>;
945 dma-requests = <3>;
948 pcie_mirror: pcie-mirror@10000400 {
949 compatible = "mediatek,mt7622-pcie-mirror",
955 compatible = "mediatek,mt7622-wed",
962 compatible = "mediatek,mt7622-wed",
969 compatible = "mediatek,mt7622-eth",
970 "mediatek,mt2701-eth",
987 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
991 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
994 cci-control-port = <&cci_control2>;
996 mediatek,pcie-mirror = <&pcie_mirror>;
998 dma-coherent;
999 #address-cells = <1>;
1000 #size-cells = <0>;
1005 compatible = "mediatek,mt7622-sgmiisys",
1008 #clock-cells = <1>;