Lines Matching +full:conf +full:- +full:mdio
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
38 sram-supply = <&mt6380_vm_reg>;
42 gpio-keys {
43 compatible = "gpio-keys";
45 factory-key {
51 wps-key {
59 compatible = "gpio-leds";
61 led-0 {
62 label = "bpi-r64:pio:green";
65 default-state = "off";
68 led-1 {
69 label = "bpi-r64:pio:red";
72 default-state = "off";
80 reg_1p8v: regulator-1p8v {
81 compatible = "regulator-fixed";
82 regulator-name = "fixed-1.8V";
83 regulator-min-microvolt = <1800000>;
84 regulator-max-microvolt = <1800000>;
85 regulator-always-on;
88 reg_3p3v: regulator-3p3v {
89 compatible = "regulator-fixed";
90 regulator-name = "fixed-3.3V";
91 regulator-min-microvolt = <3300000>;
92 regulator-max-microvolt = <3300000>;
93 regulator-boot-on;
94 regulator-always-on;
97 reg_5v: regulator-5v {
98 compatible = "regulator-fixed";
99 regulator-name = "fixed-5V";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 regulator-boot-on;
103 regulator-always-on;
116 pinctrl-names = "default";
117 pinctrl-0 = <&irrx_pins>;
124 compatible = "mediatek,eth-mac";
126 phy-mode = "2500base-x";
128 fixed-link {
130 full-duplex;
136 compatible = "mediatek,eth-mac";
138 phy-mode = "rgmii";
140 fixed-link {
142 full-duplex;
147 mdio: mdio-bus {
148 #address-cells = <1>;
149 #size-cells = <0>;
154 interrupt-controller;
155 #interrupt-cells = <1>;
156 interrupts-extended = <&pio 53 IRQ_TYPE_LEVEL_HIGH>;
157 reset-gpios = <&pio 54 0>;
160 #address-cells = <1>;
161 #size-cells = <0>;
192 phy-mode = "2500base-x";
194 fixed-link {
196 full-duplex;
207 pinctrl-names = "default";
208 pinctrl-0 = <&i2c1_pins>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&i2c2_pins>;
219 pinctrl-names = "default", "state_uhs";
220 pinctrl-0 = <&emmc_pins_default>;
221 pinctrl-1 = <&emmc_pins_uhs>;
223 bus-width = <8>;
224 max-frequency = <50000000>;
225 cap-mmc-highspeed;
226 mmc-hs200-1_8v;
227 vmmc-supply = <®_3p3v>;
228 vqmmc-supply = <®_1p8v>;
229 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
230 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
231 non-removable;
235 pinctrl-names = "default", "state_uhs";
236 pinctrl-0 = <&sd0_pins_default>;
237 pinctrl-1 = <&sd0_pins_uhs>;
239 bus-width = <4>;
240 max-frequency = <50000000>;
241 cap-sd-highspeed;
242 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
243 vmmc-supply = <®_3p3v>;
244 vqmmc-supply = <®_3p3v>;
245 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
246 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
250 pinctrl-names = "default";
251 pinctrl-0 = <¶llel_nand_pins>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&serial_nand_pins>;
264 compatible = "spi-nand";
266 spi-tx-bus-width = <4>;
267 spi-rx-bus-width = <4>;
268 nand-ecc-engine = <&snfi>;
270 compatible = "fixed-partitions";
271 #address-cells = <1>;
272 #size-cells = <1>;
277 read-only;
283 read-only;
295 pinctrl-names = "default";
296 pinctrl-0 = <&pcie0_pins>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pcie1_pins>;
308 * SATA functions. i.e. output-high: PCIe, output-low: SATA
311 gpio-hog;
313 output-high;
317 emmc_pins_default: emmc-pins-default {
327 conf-cmd-dat {
331 input-enable;
332 bias-pull-up;
335 conf-clk {
337 bias-pull-down;
341 emmc_pins_uhs: emmc-pins-uhs {
347 conf-cmd-dat {
351 input-enable;
352 drive-strength = <4>;
353 bias-pull-up;
356 conf-clk {
358 drive-strength = <4>;
359 bias-pull-down;
363 eth_pins: eth-pins {
370 i2c1_pins: i2c1-pins {
377 i2c2_pins: i2c2-pins {
384 i2s1_pins: i2s1-pins {
392 conf {
395 drive-strength = <12>;
396 bias-pull-down;
400 irrx_pins: irrx-pins {
407 irtx_pins: irtx-pins {
415 parallel_nand_pins: parallel-nand-pins {
422 pcie0_pins: pcie0-pins {
431 pcie1_pins: pcie1-pins {
440 pmic_bus_pins: pmic-bus-pins {
447 pwm_pins: pwm-pins {
459 wled_pins: wled-pins {
466 sd0_pins_default: sd0-pins-default {
476 conf-cmd-data {
479 input-enable;
480 drive-strength = <8>;
481 bias-pull-up;
483 conf-clk {
485 drive-strength = <12>;
486 bias-pull-down;
488 conf-cd {
490 bias-pull-up;
494 sd0_pins_uhs: sd0-pins-uhs {
500 conf-cmd-data {
503 input-enable;
504 bias-pull-up;
507 conf-clk {
509 bias-pull-down;
513 /* Serial NAND is shared pin with SPI-NOR */
514 serial_nand_pins: serial-nand-pins {
521 spic0_pins: spic0-pins {
528 spic1_pins: spic1-pins {
535 /* SPI-NOR is shared pin with serial NAND */
536 spi_nor_pins: spi-nor-pins {
543 /* serial NAND is shared pin with SPI-NOR */
544 serial_nand_pins: serial-nand-pins {
551 uart0_pins: uart0-pins {
558 uart2_pins: uart2-pins {
565 watchdog_pins: watchdog-pins {
574 pinctrl-names = "default";
575 pinctrl-0 = <&pwm_pins>;
580 pinctrl-names = "default";
581 pinctrl-0 = <&pmic_bus_pins>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&spic0_pins>;
601 pinctrl-names = "default";
602 pinctrl-0 = <&spic1_pins>;
606 vusb33-supply = <®_3p3v>;
607 vbus-supply = <®_5v>;
616 pinctrl-names = "default";
617 pinctrl-0 = <&uart0_pins>;
622 pinctrl-names = "default";
623 pinctrl-0 = <&uart2_pins>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&watchdog_pins>;