Lines Matching +full:axi +full:- +full:adc
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
20 #size-cells = <2>;
22 cluster0_opp: opp-table-0 {
23 compatible = "operating-points-v2";
24 opp-shared;
26 opp-hz = /bits/ 64 <598000000>;
27 opp-microvolt = <1000000>;
30 opp-hz = /bits/ 64 <702000000>;
31 opp-microvolt = <1000000>;
34 opp-hz = /bits/ 64 <793000000>;
35 opp-microvolt = <1000000>;
39 cluster1_opp: opp-table-1 {
40 compatible = "operating-points-v2";
41 opp-shared;
43 opp-hz = /bits/ 64 <598000000>;
44 opp-microvolt = <1000000>;
47 opp-hz = /bits/ 64 <702000000>;
48 opp-microvolt = <1000000>;
51 opp-hz = /bits/ 64 <793000000>;
52 opp-microvolt = <1000000>;
55 opp-hz = /bits/ 64 <897000000>;
56 opp-microvolt = <1000000>;
59 opp-hz = /bits/ 64 <1001000000>;
60 opp-microvolt = <1000000>;
65 #address-cells = <1>;
66 #size-cells = <0>;
68 cpu-map {
87 compatible = "arm,cortex-a35";
91 clock-names = "cpu", "intermediate";
92 proc-supply = <&cpus_fixed_vproc0>;
93 operating-points-v2 = <&cluster0_opp>;
94 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
99 compatible = "arm,cortex-a35";
101 enable-method = "psci";
104 clock-names = "cpu", "intermediate";
105 proc-supply = <&cpus_fixed_vproc0>;
106 operating-points-v2 = <&cluster0_opp>;
107 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
112 compatible = "arm,cortex-a72";
114 enable-method = "psci";
117 clock-names = "cpu", "intermediate";
118 proc-supply = <&cpus_fixed_vproc1>;
119 operating-points-v2 = <&cluster1_opp>;
120 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
123 idle-states {
124 entry-method = "psci";
126 CPU_SLEEP_0: cpu-sleep-0 {
127 compatible = "arm,idle-state";
128 local-timer-stop;
129 entry-latency-us = <100>;
130 exit-latency-us = <80>;
131 min-residency-us = <2000>;
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
136 compatible = "arm,idle-state";
137 local-timer-stop;
138 entry-latency-us = <350>;
139 exit-latency-us = <80>;
140 min-residency-us = <3000>;
141 arm,psci-suspend-param = <0x1010000>;
147 compatible = "arm,psci-0.2";
152 compatible = "fixed-clock";
153 clock-frequency = <26000000>;
154 #clock-cells = <0>;
158 compatible = "fixed-clock";
159 clock-frequency = <26000000>;
160 #clock-cells = <0>;
163 clk26m: oscillator-26m {
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <26000000>;
167 clock-output-names = "clk26m";
170 clk32k: oscillator-32k {
171 compatible = "fixed-clock";
172 #clock-cells = <0>;
173 clock-frequency = <32768>;
174 clock-output-names = "clk32k";
177 clkfpc: oscillator-50m {
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <50000000>;
181 clock-output-names = "clkfpc";
184 clkaud_ext_i_0: oscillator-aud0 {
185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency = <6500000>;
188 clock-output-names = "clkaud_ext_i_0";
191 clkaud_ext_i_1: oscillator-aud1 {
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <196608000>;
195 clock-output-names = "clkaud_ext_i_1";
198 clkaud_ext_i_2: oscillator-aud2 {
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <180633600>;
202 clock-output-names = "clkaud_ext_i_2";
205 clki2si0_mck_i: oscillator-i2s0 {
206 compatible = "fixed-clock";
207 #clock-cells = <0>;
208 clock-frequency = <30000000>;
209 clock-output-names = "clki2si0_mck_i";
212 clki2si1_mck_i: oscillator-i2s1 {
213 compatible = "fixed-clock";
214 #clock-cells = <0>;
215 clock-frequency = <30000000>;
216 clock-output-names = "clki2si1_mck_i";
219 clki2si2_mck_i: oscillator-i2s2 {
220 compatible = "fixed-clock";
221 #clock-cells = <0>;
222 clock-frequency = <30000000>;
223 clock-output-names = "clki2si2_mck_i";
226 clktdmin_mclk_i: oscillator-mclk {
227 compatible = "fixed-clock";
228 #clock-cells = <0>;
229 clock-frequency = <30000000>;
230 clock-output-names = "clktdmin_mclk_i";
234 compatible = "arm,armv8-timer";
235 interrupt-parent = <&gic>;
247 compatible = "mediatek,mt2712-topckgen", "syscon";
249 #clock-cells = <1>;
253 compatible = "mediatek,mt2712-infracfg", "syscon";
255 #clock-cells = <1>;
259 compatible = "mediatek,mt2712-pericfg", "syscon";
261 #clock-cells = <1>;
265 compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
270 compatible = "mediatek,mt2712-pinctrl";
272 mediatek,pctl-regmap = <&syscfg_pctl_a>;
273 gpio-controller;
274 #gpio-cells = <2>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
280 scpsys: power-controller@10006000 {
281 compatible = "mediatek,mt2712-scpsys", "syscon";
282 #power-domain-cells = <1>;
290 clock-names = "mm", "mfg", "venc",
296 compatible = "mediatek,mt2712-uart",
297 "mediatek,mt6577-uart";
301 clock-names = "baud", "bus";
304 dma-names = "tx", "rx";
309 compatible = "mediatek,mt2712-rtc";
315 compatible = "mediatek,mt2712-spi-slave";
319 clock-names = "spi";
320 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
321 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
326 compatible = "mediatek,mt2712-m4u";
330 clock-names = "bclk";
334 #iommu-cells = <1>;
338 compatible = "mediatek,mt2712-apmixedsys", "syscon";
340 #clock-cells = <1>;
344 compatible = "mediatek,mt2712-m4u";
348 clock-names = "bclk";
351 #iommu-cells = <1>;
355 compatible = "mediatek,mt2712-mcucfg", "syscon";
357 #clock-cells = <1>;
360 sysirq: interrupt-controller@10220a80 {
361 compatible = "mediatek,mt2712-sysirq",
362 "mediatek,mt6577-sysirq";
363 interrupt-controller;
364 #interrupt-cells = <3>;
365 interrupt-parent = <&gic>;
369 gic: interrupt-controller@10510000 {
370 compatible = "arm,gic-400";
371 #interrupt-cells = <3>;
372 interrupt-parent = <&gic>;
373 interrupt-controller;
382 apdma: dma-controller@11000400 {
383 compatible = "mediatek,mt2712-uart-dma",
384 "mediatek,mt6577-uart-dma";
409 dma-requests = <12>;
411 clock-names = "apdma";
412 #dma-cells = <1>;
415 auxadc: adc@11001000 {
416 compatible = "mediatek,mt2712-auxadc";
419 clock-names = "main";
420 #io-channel-cells = <1>;
425 compatible = "mediatek,mt2712-uart",
426 "mediatek,mt6577-uart";
430 clock-names = "baud", "bus";
433 dma-names = "tx", "rx";
438 compatible = "mediatek,mt2712-uart",
439 "mediatek,mt6577-uart";
443 clock-names = "baud", "bus";
446 dma-names = "tx", "rx";
451 compatible = "mediatek,mt2712-uart",
452 "mediatek,mt6577-uart";
456 clock-names = "baud", "bus";
459 dma-names = "tx", "rx";
464 compatible = "mediatek,mt2712-uart",
465 "mediatek,mt6577-uart";
469 clock-names = "baud", "bus";
472 dma-names = "tx", "rx";
477 compatible = "mediatek,mt2712-pwm";
479 #pwm-cells = <2>;
491 clock-names = "top",
505 compatible = "mediatek,mt2712-i2c";
509 clock-div = <4>;
512 clock-names = "main",
514 #address-cells = <1>;
515 #size-cells = <0>;
520 compatible = "mediatek,mt2712-i2c";
524 clock-div = <4>;
527 clock-names = "main",
529 #address-cells = <1>;
530 #size-cells = <0>;
535 compatible = "mediatek,mt2712-i2c";
539 clock-div = <4>;
542 clock-names = "main",
544 #address-cells = <1>;
545 #size-cells = <0>;
550 compatible = "mediatek,mt2712-spi";
551 #address-cells = <1>;
552 #size-cells = <0>;
558 clock-names = "parent-clk", "sel-clk", "spi-clk";
562 nandc: nand-controller@1100e000 {
563 compatible = "mediatek,mt2712-nfc";
567 clock-names = "nfi_clk", "pad_clk";
568 ecc-engine = <&bch>;
569 #address-cells = <1>;
570 #size-cells = <0>;
575 compatible = "mediatek,mt2712-ecc";
579 clock-names = "nfiecc_clk";
584 compatible = "mediatek,mt2712-i2c";
588 clock-div = <4>;
591 clock-names = "main",
593 #address-cells = <1>;
594 #size-cells = <0>;
599 compatible = "mediatek,mt2712-i2c";
603 clock-div = <4>;
606 clock-names = "main",
608 #address-cells = <1>;
609 #size-cells = <0>;
614 compatible = "mediatek,mt2712-i2c";
618 clock-div = <4>;
621 clock-names = "main",
623 #address-cells = <1>;
624 #size-cells = <0>;
629 compatible = "mediatek,mt2712-spi";
630 #address-cells = <1>;
631 #size-cells = <0>;
637 clock-names = "parent-clk", "sel-clk", "spi-clk";
642 compatible = "mediatek,mt2712-spi";
643 #address-cells = <1>;
644 #size-cells = <0>;
650 clock-names = "parent-clk", "sel-clk", "spi-clk";
655 compatible = "mediatek,mt2712-spi";
656 #address-cells = <1>;
657 #size-cells = <0>;
663 clock-names = "parent-clk", "sel-clk", "spi-clk";
668 compatible = "mediatek,mt2712-spi";
669 #address-cells = <1>;
670 #size-cells = <0>;
676 clock-names = "parent-clk", "sel-clk", "spi-clk";
681 compatible = "mediatek,mt2712-uart",
682 "mediatek,mt6577-uart";
686 clock-names = "baud", "bus";
689 dma-names = "tx", "rx";
693 stmmac_axi_setup: stmmac-axi-config {
699 mtl_rx_setup: rx-queues-config {
700 snps,rx-queues-to-use = <1>;
701 snps,rx-sched-sp;
703 snps,dcb-algorithm;
704 snps,map-to-dma-channel = <0x0>;
709 mtl_tx_setup: tx-queues-config {
710 snps,tx-queues-to-use = <3>;
711 snps,tx-sched-wrr;
714 snps,dcb-algorithm;
719 snps,dcb-algorithm;
724 snps,dcb-algorithm;
730 compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
733 interrupt-names = "macirq";
734 mac-address = [00 55 7b b5 7d f7];
735 clock-names = "axi",
745 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
748 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
751 power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
753 snps,axi-config = <&stmmac_axi_setup>;
754 snps,mtl-rx-config = <&mtl_rx_setup>;
755 snps,mtl-tx-config = <&mtl_tx_setup>;
758 snps,clk-csr = <0>;
763 compatible = "mediatek,mt2712-mmc";
770 clock-names = "source", "hclk", "source_cg", "bus_clk";
775 compatible = "mediatek,mt2712-mmc";
781 clock-names = "source", "hclk", "source_cg";
786 compatible = "mediatek,mt2712-mmc";
792 clock-names = "source", "hclk", "source_cg";
797 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
800 reg-names = "mac", "ippc";
804 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
806 clock-names = "sys_ck";
807 mediatek,syscon-wakeup = <&pericfg 0x510 2>;
808 #address-cells = <2>;
809 #size-cells = <2>;
814 compatible = "mediatek,mt2712-xhci",
815 "mediatek,mtk-xhci";
817 reg-names = "mac";
819 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
821 clock-names = "sys_ck", "ref_ck";
826 u3phy0: t-phy@11290000 {
827 compatible = "mediatek,mt2712-tphy",
828 "mediatek,generic-tphy-v2";
829 #address-cells = <1>;
830 #size-cells = <1>;
834 u2port0: usb-phy@0 {
837 clock-names = "ref";
838 #phy-cells = <1>;
842 u2port1: usb-phy@8000 {
845 clock-names = "ref";
846 #phy-cells = <1>;
850 u3port0: usb-phy@8700 {
853 clock-names = "ref";
854 #phy-cells = <1>;
860 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
863 reg-names = "mac", "ippc";
868 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
870 clock-names = "sys_ck";
871 mediatek,syscon-wakeup = <&pericfg 0x514 2>;
872 #address-cells = <2>;
873 #size-cells = <2>;
878 compatible = "mediatek,mt2712-xhci",
879 "mediatek,mtk-xhci";
881 reg-names = "mac";
883 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
885 clock-names = "sys_ck", "ref_ck";
890 u3phy1: t-phy@112e0000 {
891 compatible = "mediatek,mt2712-tphy",
892 "mediatek,generic-tphy-v2";
893 #address-cells = <1>;
894 #size-cells = <1>;
898 u2port2: usb-phy@0 {
901 clock-names = "ref";
902 #phy-cells = <1>;
906 u2port3: usb-phy@8000 {
909 clock-names = "ref";
910 #phy-cells = <1>;
914 u3port1: usb-phy@8700 {
917 clock-names = "ref";
918 #phy-cells = <1>;
924 compatible = "mediatek,mt2712-pcie";
927 reg-names = "port1";
928 linux,pci-domain = <1>;
929 #address-cells = <3>;
930 #size-cells = <2>;
932 interrupt-names = "pcie_irq";
935 clock-names = "sys_ck1", "ahb_ck1";
937 phy-names = "pcie-phy1";
938 bus-range = <0x00 0xff>;
942 #interrupt-cells = <1>;
943 interrupt-map-mask = <0 0 0 7>;
944 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
948 pcie_intc1: interrupt-controller {
949 interrupt-controller;
950 #address-cells = <0>;
951 #interrupt-cells = <1>;
956 compatible = "mediatek,mt2712-pcie";
959 reg-names = "port0";
960 linux,pci-domain = <0>;
961 #address-cells = <3>;
962 #size-cells = <2>;
964 interrupt-names = "pcie_irq";
967 clock-names = "sys_ck0", "ahb_ck0";
969 phy-names = "pcie-phy0";
970 bus-range = <0x00 0xff>;
974 #interrupt-cells = <1>;
975 interrupt-map-mask = <0 0 0 7>;
976 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
980 pcie_intc0: interrupt-controller {
981 interrupt-controller;
982 #address-cells = <0>;
983 #interrupt-cells = <1>;
988 compatible = "mediatek,mt2712-mfgcfg", "syscon";
990 #clock-cells = <1>;
994 compatible = "mediatek,mt2712-mmsys", "syscon";
996 #clock-cells = <1>;
1000 compatible = "mediatek,mt2712-smi-larb";
1003 mediatek,larb-id = <0>;
1004 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1007 clock-names = "apb", "smi";
1011 compatible = "mediatek,mt2712-smi-common";
1013 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1016 clock-names = "apb", "smi";
1020 compatible = "mediatek,mt2712-smi-larb";
1023 mediatek,larb-id = <4>;
1024 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1027 clock-names = "apb", "smi";
1031 compatible = "mediatek,mt2712-smi-larb";
1034 mediatek,larb-id = <5>;
1035 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1038 clock-names = "apb", "smi";
1042 compatible = "mediatek,mt2712-smi-common";
1044 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1047 clock-names = "apb", "smi";
1051 compatible = "mediatek,mt2712-smi-larb";
1054 mediatek,larb-id = <7>;
1055 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1058 clock-names = "apb", "smi";
1062 compatible = "mediatek,mt2712-imgsys", "syscon";
1064 #clock-cells = <1>;
1068 compatible = "mediatek,mt2712-smi-larb";
1071 mediatek,larb-id = <2>;
1072 power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>;
1075 clock-names = "apb", "smi";
1079 compatible = "mediatek,mt2712-bdpsys", "syscon";
1081 #clock-cells = <1>;
1085 compatible = "mediatek,mt2712-vdecsys", "syscon";
1087 #clock-cells = <1>;
1091 compatible = "mediatek,mt2712-smi-larb";
1094 mediatek,larb-id = <1>;
1095 power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>;
1098 clock-names = "apb", "smi";
1102 compatible = "mediatek,mt2712-vencsys", "syscon";
1104 #clock-cells = <1>;
1108 compatible = "mediatek,mt2712-smi-larb";
1111 mediatek,larb-id = <3>;
1112 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1115 clock-names = "apb", "smi";
1119 compatible = "mediatek,mt2712-smi-larb";
1122 mediatek,larb-id = <6>;
1123 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1126 clock-names = "apb", "smi";
1130 compatible = "mediatek,mt2712-jpgdecsys", "syscon";
1132 #clock-cells = <1>;