Lines Matching +full:0 +full:x11007000
22 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
154 #clock-cells = <0>;
160 #clock-cells = <0>;
165 #clock-cells = <0>;
172 #clock-cells = <0>;
179 #clock-cells = <0>;
186 #clock-cells = <0>;
193 #clock-cells = <0>;
200 #clock-cells = <0>;
207 #clock-cells = <0>;
214 #clock-cells = <0>;
221 #clock-cells = <0>;
228 #clock-cells = <0>;
237 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
239 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
241 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
243 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
248 reg = <0 0x10000000 0 0x1000>;
254 reg = <0 0x10001000 0 0x1000>;
260 reg = <0 0x10003000 0 0x1000>;
266 reg = <0 0x10005000 0 0x1000>;
271 reg = <0 0x1000b000 0 0x1000>;
283 reg = <0 0x10006000 0 0x1000>;
298 reg = <0 0x1000f000 0 0x400>;
310 reg = <0 0x10011000 0 0x1000>;
316 reg = <0 0x10013000 0 0x100>;
327 reg = <0 0x10205000 0 0x1000>;
339 reg = <0 0x10209000 0 0x1000>;
345 reg = <0 0x1020a000 0 0x1000>;
356 reg = <0 0x10220000 0 0x1000>;
366 reg = <0 0x10220a80 0 0x40>;
374 reg = <0 0x10510000 0 0x10000>,
375 <0 0x10520000 0 0x20000>,
376 <0 0x10540000 0 0x20000>,
377 <0 0x10560000 0 0x20000>;
379 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
385 reg = <0 0x11000400 0 0x80>,
386 <0 0x11000480 0 0x80>,
387 <0 0x11000500 0 0x80>,
388 <0 0x11000580 0 0x80>,
389 <0 0x11000600 0 0x80>,
390 <0 0x11000680 0 0x80>,
391 <0 0x11000700 0 0x80>,
392 <0 0x11000780 0 0x80>,
393 <0 0x11000800 0 0x80>,
394 <0 0x11000880 0 0x80>,
395 <0 0x11000900 0 0x80>,
396 <0 0x11000980 0 0x80>;
417 reg = <0 0x11001000 0 0x1000>;
427 reg = <0 0x11002000 0 0x400>;
431 dmas = <&apdma 0
440 reg = <0 0x11003000 0 0x400>;
453 reg = <0 0x11004000 0 0x400>;
466 reg = <0 0x11005000 0 0x400>;
478 reg = <0 0x11006000 0 0x1000>;
506 reg = <0 0x11007000 0 0x90>,
507 <0 0x11000180 0 0x80>;
515 #size-cells = <0>;
521 reg = <0 0x11008000 0 0x90>,
522 <0 0x11000200 0 0x80>;
530 #size-cells = <0>;
536 reg = <0 0x11009000 0 0x90>,
537 <0 0x11000280 0 0x80>;
545 #size-cells = <0>;
552 #size-cells = <0>;
553 reg = <0 0x1100a000 0 0x100>;
564 reg = <0 0x1100e000 0 0x1000>;
570 #size-cells = <0>;
576 reg = <0 0x1100f000 0 0x1000>;
585 reg = <0 0x11010000 0 0x90>,
586 <0 0x11000300 0 0x80>;
594 #size-cells = <0>;
600 reg = <0 0x11011000 0 0x90>,
601 <0 0x11000380 0 0x80>;
609 #size-cells = <0>;
615 reg = <0 0x11013000 0 0x90>,
616 <0 0x11000100 0 0x80>;
624 #size-cells = <0>;
631 #size-cells = <0>;
632 reg = <0 0x11015000 0 0x100>;
644 #size-cells = <0>;
645 reg = <0 0x11016000 0 0x100>;
657 #size-cells = <0>;
658 reg = <0 0x10012000 0 0x100>;
670 #size-cells = <0>;
671 reg = <0 0x11018000 0 0x100>;
683 reg = <0 0x11019000 0 0x400>;
694 snps,wr_osr_lmt = <0x7>;
695 snps,rd_osr_lmt = <0x7>;
696 snps,blen = <0 0 0 0 16 8 4>;
704 snps,map-to-dma-channel = <0x0>;
705 snps,priority = <0x0>;
713 snps,weight = <0x10>;
715 snps,priority = <0x0>;
718 snps,weight = <0x11>;
720 snps,priority = <0x1>;
723 snps,weight = <0x12>;
725 snps,priority = <0x2>;
731 reg = <0 0x1101c000 0 0x1300>;
758 snps,clk-csr = <0>;
764 reg = <0 0x11230000 0 0x1000>;
776 reg = <0 0x11240000 0 0x1000>;
787 reg = <0 0x11250000 0 0x1000>;
798 reg = <0 0x11271000 0 0x3000>,
799 <0 0x11280700 0 0x0100>;
807 mediatek,syscon-wakeup = <&pericfg 0x510 2>;
816 reg = <0 0x11270000 0 0x1000>;
831 ranges = <0 0 0x11290000 0x9000>;
834 u2port0: usb-phy@0 {
835 reg = <0x0 0x700>;
843 reg = <0x8000 0x700>;
851 reg = <0x8700 0x900>;
861 reg = <0 0x112c1000 0 0x3000>,
862 <0 0x112d0700 0 0x0100>;
871 mediatek,syscon-wakeup = <&pericfg 0x514 2>;
880 reg = <0 0x112c0000 0 0x1000>;
895 ranges = <0 0 0x112e0000 0x9000>;
898 u2port2: usb-phy@0 {
899 reg = <0x0 0x700>;
907 reg = <0x8000 0x700>;
915 reg = <0x8700 0x900>;
926 reg = <0 0x112ff000 0 0x1000>;
938 bus-range = <0x00 0xff>;
939 ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
943 interrupt-map-mask = <0 0 0 7>;
944 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
945 <0 0 0 2 &pcie_intc1 1>,
946 <0 0 0 3 &pcie_intc1 2>,
947 <0 0 0 4 &pcie_intc1 3>;
950 #address-cells = <0>;
958 reg = <0 0x11700000 0 0x1000>;
960 linux,pci-domain = <0>;
970 bus-range = <0x00 0xff>;
971 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
975 interrupt-map-mask = <0 0 0 7>;
976 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
977 <0 0 0 2 &pcie_intc0 1>,
978 <0 0 0 3 &pcie_intc0 2>,
979 <0 0 0 4 &pcie_intc0 3>;
982 #address-cells = <0>;
989 reg = <0 0x13000000 0 0x1000>;
995 reg = <0 0x14000000 0 0x1000>;
1001 reg = <0 0x14021000 0 0x1000>;
1003 mediatek,larb-id = <0>;
1012 reg = <0 0x14022000 0 0x1000>;
1021 reg = <0 0x14027000 0 0x1000>;
1032 reg = <0 0x14030000 0 0x1000>;
1043 reg = <0 0x14031000 0 0x1000>;
1052 reg = <0 0x14032000 0 0x1000>;
1063 reg = <0 0x15000000 0 0x1000>;
1069 reg = <0 0x15001000 0 0x1000>;
1080 reg = <0 0x15010000 0 0x1000>;
1086 reg = <0 0x16000000 0 0x1000>;
1092 reg = <0 0x16010000 0 0x1000>;
1103 reg = <0 0x18000000 0 0x1000>;
1109 reg = <0 0x18001000 0 0x1000>;
1120 reg = <0 0x18002000 0 0x1000>;
1131 reg = <0 0x19000000 0 0x1000>;