Lines Matching +full:pcie2 +full:- +full:phy
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
48 #address-cells = <2>;
49 #size-cells = <2>;
50 compatible = "simple-bus";
51 interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
54 config-space@CP11X_BASE {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "simple-bus";
61 #address-cells = <1>;
62 #size-cells = <0>;
63 compatible = "marvell,armada-7k-pp22";
68 clock-names = "pp_clk", "gop_clk",
70 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
72 dma-coherent;
74 CP11X_LABEL(eth0): ethernet-port@0 {
85 interrupt-names = "hif0", "hif1", "hif2",
89 port-id = <0>; /* For backward compatibility. */
90 gop-port-id = <0>;
94 CP11X_LABEL(eth1): ethernet-port@1 {
105 interrupt-names = "hif0", "hif1", "hif2",
109 port-id = <1>; /* For backward compatibility. */
110 gop-port-id = <2>;
114 CP11X_LABEL(eth2): ethernet-port@2 {
125 interrupt-names = "hif0", "hif1", "hif2",
129 port-id = <2>; /* For backward compatibility. */
130 gop-port-id = <3>;
135 CP11X_LABEL(comphy): phy@120000 {
136 compatible = "marvell,comphy-cp110";
138 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
141 clock-names = "mg_clk", "mg_core_clk", "axi_clk";
142 #address-cells = <1>;
143 #size-cells = <0>;
145 CP11X_LABEL(comphy0): phy@0 {
147 #phy-cells = <1>;
150 CP11X_LABEL(comphy1): phy@1 {
152 #phy-cells = <1>;
155 CP11X_LABEL(comphy2): phy@2 {
157 #phy-cells = <1>;
160 CP11X_LABEL(comphy3): phy@3 {
162 #phy-cells = <1>;
165 CP11X_LABEL(comphy4): phy@4 {
167 #phy-cells = <1>;
170 CP11X_LABEL(comphy5): phy@5 {
172 #phy-cells = <1>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 compatible = "marvell,orion-mdio";
187 #address-cells = <1>;
188 #size-cells = <0>;
196 CP11X_LABEL(icu): interrupt-controller@1e0000 {
197 compatible = "marvell,cp110-icu";
199 #address-cells = <1>;
200 #size-cells = <1>;
202 CP11X_LABEL(icu_nsr): interrupt-controller@10 {
203 compatible = "marvell,cp110-icu-nsr";
205 #interrupt-cells = <2>;
206 interrupt-controller;
207 msi-parent = <&gicp>;
210 CP11X_LABEL(icu_sei): interrupt-controller@50 {
211 compatible = "marvell,cp110-icu-sei";
213 #interrupt-cells = <2>;
214 interrupt-controller;
215 msi-parent = <&sei>;
220 compatible = "marvell,armada-8k-rtc";
222 reg-names = "rtc", "rtc-soc";
226 CP11X_LABEL(syscon0): system-controller@440000 {
227 compatible = "syscon", "simple-mfd";
231 compatible = "marvell,cp110-clock";
232 #clock-cells = <2>;
236 compatible = "marvell,armada-8k-gpio";
239 gpio-controller;
240 #gpio-cells = <2>;
241 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
242 marvell,pwm-offset = <0x1f0>;
243 #pwm-cells = <2>;
244 interrupt-controller;
249 #interrupt-cells = <2>;
250 clock-names = "core", "axi";
257 compatible = "marvell,armada-8k-gpio";
260 gpio-controller;
261 #gpio-cells = <2>;
262 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
263 marvell,pwm-offset = <0x1f0>;
264 #pwm-cells = <2>;
265 interrupt-controller;
270 #interrupt-cells = <2>;
271 clock-names = "core", "axi";
278 CP11X_LABEL(syscon1): system-controller@400000 {
279 compatible = "syscon", "simple-mfd";
281 #address-cells = <1>;
282 #size-cells = <1>;
284 CP11X_LABEL(thermal): thermal-sensor@70 {
285 compatible = "marvell,armada-cp110-thermal";
287 interrupts-extended =
289 #thermal-sensor-cells = <1>;
294 compatible = "marvell,cp110-utmi-phy";
296 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
297 #address-cells = <1>;
298 #size-cells = <0>;
301 CP11X_LABEL(utmi0): usb-phy@0 {
303 #phy-cells = <0>;
306 CP11X_LABEL(utmi1): usb-phy@1 {
308 #phy-cells = <0>;
313 compatible = "marvell,armada-8k-xhci",
314 "generic-xhci";
316 dma-coherent;
318 clock-names = "core", "reg";
325 compatible = "marvell,armada-8k-xhci",
326 "generic-xhci";
328 dma-coherent;
330 clock-names = "core", "reg";
337 compatible = "marvell,armada-8k-ahci",
338 "generic-ahci";
340 dma-coherent;
344 #address-cells = <1>;
345 #size-cells = <0>;
348 sata-port@0 {
352 sata-port@1 {
358 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
360 dma-coherent;
361 msi-parent = <&gic_v2m0>;
362 clock-names = "core", "reg";
368 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
370 dma-coherent;
371 msi-parent = <&gic_v2m0>;
372 clock-names = "core", "reg";
378 compatible = "marvell,armada-380-spi";
380 #address-cells = <0x1>;
381 #size-cells = <0x0>;
382 clock-names = "core", "axi";
389 compatible = "marvell,armada-380-spi";
391 #address-cells = <1>;
392 #size-cells = <0>;
393 clock-names = "core", "axi";
400 compatible = "marvell,mv78230-i2c";
402 #address-cells = <1>;
403 #size-cells = <0>;
405 clock-names = "core", "reg";
412 compatible = "marvell,mv78230-i2c";
414 #address-cells = <1>;
415 #size-cells = <0>;
417 clock-names = "core", "reg";
424 compatible = "snps,dw-apb-uart";
426 reg-shift = <2>;
428 reg-io-width = <1>;
429 clock-names = "baudclk", "apb_pclk";
436 compatible = "snps,dw-apb-uart";
438 reg-shift = <2>;
440 reg-io-width = <1>;
441 clock-names = "baudclk", "apb_pclk";
448 compatible = "snps,dw-apb-uart";
450 reg-shift = <2>;
452 reg-io-width = <1>;
453 clock-names = "baudclk", "apb_pclk";
460 compatible = "snps,dw-apb-uart";
462 reg-shift = <2>;
464 reg-io-width = <1>;
465 clock-names = "baudclk", "apb_pclk";
471 CP11X_LABEL(nand_controller): nand-controller@720000 {
477 compatible = "marvell,armada-8k-nand-controller",
478 "marvell,armada370-nand-controller";
480 #address-cells = <1>;
481 #size-cells = <0>;
483 clock-names = "core", "reg";
486 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
491 compatible = "marvell,armada-8k-rng",
492 "inside-secure,safexcel-eip76";
495 clock-names = "core", "reg";
502 compatible = "marvell,armada-cp110-sdhci";
505 clock-names = "core", "axi";
507 dma-coherent;
512 compatible = "inside-secure,safexcel-eip197b";
520 interrupt-names = "mem", "ring0", "ring1",
522 clock-names = "core", "reg";
525 dma-coherent;
530 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
533 reg-names = "ctrl", "config";
534 #address-cells = <3>;
535 #size-cells = <2>;
536 #interrupt-cells = <1>;
538 dma-coherent;
539 msi-parent = <&gic_v2m0>;
541 bus-range = <0 0xff>;
542 /* non-prefetchable memory */
544 interrupt-map-mask = <0 0 0 0>;
545 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
547 num-lanes = <1>;
548 clock-names = "core", "reg";
554 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
557 reg-names = "ctrl", "config";
558 #address-cells = <3>;
559 #size-cells = <2>;
560 #interrupt-cells = <1>;
562 dma-coherent;
563 msi-parent = <&gic_v2m0>;
565 bus-range = <0 0xff>;
566 /* non-prefetchable memory */
568 interrupt-map-mask = <0 0 0 0>;
569 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
572 num-lanes = <1>;
573 clock-names = "core", "reg";
578 CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
579 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
582 reg-names = "ctrl", "config";
583 #address-cells = <3>;
584 #size-cells = <2>;
585 #interrupt-cells = <1>;
587 dma-coherent;
588 msi-parent = <&gic_v2m0>;
590 bus-range = <0 0xff>;
591 /* non-prefetchable memory */
593 interrupt-map-mask = <0 0 0 0>;
594 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
597 num-lanes = <1>;
598 clock-names = "core", "reg";