Lines Matching +full:0 +full:x080
16 reg = <0x0 0xe896c000 0x0 0x72c>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
22 pinctrl-single,gpio-range = <&range 0 82 0>;
26 0x054 MUX_M2 /* UART0_RXD */
27 0x058 MUX_M2 /* UART0_TXD */
33 0x700 MUX_M2 /* UART2_CTS_N */
34 0x704 MUX_M2 /* UART2_RTS_N */
35 0x708 MUX_M2 /* UART2_RXD */
36 0x70c MUX_M2 /* UART2_TXD */
42 0x064 MUX_M1 /* UART3_CTS_N */
43 0x068 MUX_M1 /* UART3_RTS_N */
44 0x06c MUX_M1 /* UART3_RXD */
45 0x070 MUX_M1 /* UART3_TXD */
51 0x074 MUX_M1 /* UART4_CTS_N */
52 0x078 MUX_M1 /* UART4_RTS_N */
53 0x07c MUX_M1 /* UART4_RXD */
54 0x080 MUX_M1 /* UART4_TXD */
60 0x05c MUX_M1 /* UART6_RXD */
61 0x060 MUX_M1 /* UART6_TXD */
67 0x010 MUX_M1 /* I2C3_SCL */
68 0x014 MUX_M1 /* I2C3_SDA */
74 0x03c MUX_M1 /* I2C4_SCL */
75 0x040 MUX_M1 /* I2C4_SDA */
81 0x714 MUX_M0 /* CAM0_RST */
87 0x048 MUX_M0 /* CAM1_RST */
93 0x098 MUX_M0 /* CAM0_PWD_N */
99 0x044 MUX_M0 /* CAM1_PWD_N */
105 0x018 MUX_M1 /* ISP_CLK0 */
106 0x024 MUX_M1 /* ISP_SCL0 */
107 0x028 MUX_M1 /* ISP_SDA0 */
113 0x01c MUX_M1 /* ISP_CLK1 */
114 0x02c MUX_M1 /* ISP_SCL1 */
115 0x030 MUX_M1 /* ISP_SDA1 */
122 reg = <0x0 0xfff11000 0x0 0x73c>;
123 #gpio-range-cells = <0x3>;
125 pinctrl-single,register-width = <0x20>;
126 pinctrl-single,function-mask = <0x7>;
128 pinctrl-single,gpio-range = <&range 0 46 0>;
132 0x064 MUX_M0 /* GPIO_203 */
138 0x080 MUX_M0 /* GPIO_221 */
144 0x050 MUX_M1 /* I2S2_DI */
145 0x054 MUX_M1 /* I2S2_DO */
146 0x058 MUX_M1 /* I2S2_XCLK */
147 0x05c MUX_M1 /* I2S2_XFS */
153 0x094 MUX_M1 /* SPI0_CLK */
154 0x098 MUX_M1 /* SPI0_DI */
155 0x09c MUX_M1 /* SPI0_DO */
156 0x0a0 MUX_M1 /* SPI0_CS0_N */
162 0x710 MUX_M1 /* SPI2_CLK */
163 0x714 MUX_M1 /* SPI2_DI */
164 0x718 MUX_M1 /* SPI2_DO */
165 0x71c MUX_M1 /* SPI2_CS0_N */
171 0x72c MUX_M1 /* SPI3_CLK */
172 0x730 MUX_M1 /* SPI3_DI */
173 0x734 MUX_M1 /* SPI3_DO */
174 0x738 MUX_M1 /* SPI3_CS0_N */
180 0x020 MUX_M1 /* I2C0_SCL */
181 0x024 MUX_M1 /* I2C0_SDA */
187 0x028 MUX_M1 /* I2C1_SCL */
188 0x02c MUX_M1 /* I2C1_SDA */
193 0x030 MUX_M1 /* I2C2_SCL */
194 0x034 MUX_M1 /* I2C2_SDA */
200 0x084 MUX_M1 /* PCIE0_CLKREQ_N */
205 pinctrl-single,pins = <0x01C 0x1>;
209 pinctrl-single,pins = <0x01C 0x0>;
215 reg = <0x0 0xe896c800 0x0 0x72c>;
217 pinctrl-single,register-width = <0x20>;
221 0x058 0x0 /* UART0_RXD */
222 0x05c 0x0 /* UART0_TXD */
243 0x700 0x0 /* UART2_CTS_N */
244 0x704 0x0 /* UART2_RTS_N */
245 0x708 0x0 /* UART2_RXD */
246 0x70c 0x0 /* UART2_TXD */
267 0x068 0x0 /* UART3_CTS_N */
268 0x06c 0x0 /* UART3_RTS_N */
269 0x070 0x0 /* UART3_RXD */
270 0x074 0x0 /* UART3_TXD */
291 0x078 0x0 /* UART4_CTS_N */
292 0x07c 0x0 /* UART4_RTS_N */
293 0x080 0x0 /* UART4_RXD */
294 0x084 0x0 /* UART4_TXD */
315 0x060 0x0 /* UART6_RXD */
316 0x064 0x0 /* UART6_TXD */
337 0x014 0x0 /* I2C3_SCL */
338 0x018 0x0 /* I2C3_SDA */
359 0x040 0x0 /* I2C4_SCL */
360 0x044 0x0 /* I2C4_SDA */
381 0x714 0x0 /* CAM0_RST */
402 0x04C 0x0 /* CAM1_RST */
423 0x09C 0x0 /* CAM0_PWD_N */
444 0x048 0x0 /* CAM1_PWD_N */
465 0x01C 0x0 /* ISP_CLK0 */
466 0x028 0x0 /* ISP_SCL0 */
467 0x02C 0x0 /* ISP_SDA0 */
488 0x020 0x0 /* ISP_CLK1 */
489 0x030 0x0 /* ISP_SCL1 */
490 0x034 0x0 /* ISP_SDA1 */
512 reg = <0x0 0xfc182000 0x0 0x028>;
515 pinctrl-single,register-width = <0x20>;
516 pinctrl-single,function-mask = <0x7>;
518 pinctrl-single,gpio-range = <&range 0 10 0>;
522 0x000 MUX_M1 /* SDIO_CLK */
523 0x004 MUX_M1 /* SDIO_CMD */
524 0x008 MUX_M1 /* SDIO_DATA0 */
525 0x00c MUX_M1 /* SDIO_DATA1 */
526 0x010 MUX_M1 /* SDIO_DATA2 */
527 0x014 MUX_M1 /* SDIO_DATA3 */
534 reg = <0x0 0xfc182800 0x0 0x028>;
536 pinctrl-single,register-width = <0x20>;
540 0x000 0x0 /* SDIO_CLK */
561 0x004 0x0 /* SDIO_CMD */
562 0x008 0x0 /* SDIO_DATA0 */
563 0x00c 0x0 /* SDIO_DATA1 */
564 0x010 0x0 /* SDIO_DATA2 */
565 0x014 0x0 /* SDIO_DATA3 */
587 reg = <0x0 0xff37e000 0x0 0x030>;
590 pinctrl-single,register-width = <0x20>;
593 pinctrl-single,gpio-range = <&range 0 12 0>;
597 0x000 MUX_M1 /* SD_CLK */
598 0x004 MUX_M1 /* SD_CMD */
599 0x008 MUX_M1 /* SD_DATA0 */
600 0x00c MUX_M1 /* SD_DATA1 */
601 0x010 MUX_M1 /* SD_DATA2 */
602 0x014 MUX_M1 /* SD_DATA3 */
609 reg = <0x0 0xff37e800 0x0 0x030>;
611 pinctrl-single,register-width = <0x20>;
615 0x000 0x0 /* SD_CLK */
637 0x004 0x0 /* SD_CMD */
638 0x008 0x0 /* SD_DATA0 */
639 0x00c 0x0 /* SD_DATA1 */
640 0x010 0x0 /* SD_DATA2 */
641 0x014 0x0 /* SD_DATA3 */
664 reg = <0x0 0xfff11800 0x0 0x73c>;
666 pinctrl-single,register-width = <0x20>;
670 0x090 0x0 /* GPIO_203 */
691 0x0AC 0x0 /* GPIO_221 */
712 0x0c8 0x0 /* SPI0_DI */
713 0x0cc 0x0 /* SPI0_DO */
714 0x0d0 0x0 /* SPI0_CS0_N */
735 0x714 0x0 /* SPI2_DI */
736 0x718 0x0 /* SPI2_DO */
737 0x71c 0x0 /* SPI2_CS0_N */
758 0x730 0x0 /* SPI3_DI */
759 0x734 0x0 /* SPI3_DO */
760 0x738 0x0 /* SPI3_CS0_N */
781 0x0c4 0x0 /* SPI0_CLK */
802 0x710 0x0 /* SPI2_CLK */
823 0x72c 0x0 /* SPI3_CLK */
844 0x04c 0x0 /* I2C0_SCL */
845 0x050 0x0 /* I2C0_SDA */
866 0x054 0x0 /* I2C1_SCL */
867 0x058 0x0 /* I2C1_SDA */
888 0x05c 0x0 /* I2C2_SCL */
889 0x060 0x0 /* I2C2_SDA */
910 0x0b0 0x0
930 0x07c 0x0 /* I2S2_DI */
931 0x080 0x0 /* I2S2_DO */
932 0x084 0x0 /* I2S2_XCLK */
933 0x088 0x0 /* I2S2_XFS */
953 pinctrl-single,pins = <0x048 0>;
954 pinctrl-single,bias-pulldown = <0 2 0 2>;
955 pinctrl-single,bias-pullup = <0 1 0 1>;
956 pinctrl-single,drive-strength = <0x00 0x70>;
957 pinctrl-single,slew-rate = <0x0 0x80>;
961 pinctrl-single,pins = <0x048 0>;
962 pinctrl-single,bias-pulldown = <2 2 0 2>;
963 pinctrl-single,bias-pullup = <0 1 0 1>;
964 pinctrl-single,drive-strength = <0x00 0x70>;
965 pinctrl-single,slew-rate = <0x0 0x80>;