Lines Matching +full:0 +full:x18c
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x0 0x0>;
34 d-cache-size = <0x8000>; /* 32 KiB */
37 i-cache-size = <0x8000>; /* 32 KiB */
46 reg = <0x0 0x1>;
48 d-cache-size = <0x8000>; /* 32 KiB */
51 i-cache-size = <0x8000>; /* 32 KiB */
60 reg = <0x0 0x2>;
62 d-cache-size = <0x8000>; /* 32 KiB */
65 i-cache-size = <0x8000>; /* 32 KiB */
74 reg = <0x0 0x3>;
76 d-cache-size = <0x8000>; /* 32 KiB */
79 i-cache-size = <0x8000>; /* 32 KiB */
89 cache-size = <0x80000>; /* 512 KiB */
97 reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
98 <0x0 0xf1002000 0x0 0x2000>, /* GICC */
99 <0x0 0xf1004000 0x0 0x2000>, /* GICH */
100 <0x0 0xf1006000 0x0 0x2000>; /* GICV */
103 #address-cells = <0>;
124 ranges = <0x0 0x0 0xf0000000 0x10000000>;
128 reg = <0x8a22000 0x1000>;
136 0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)
137 0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)
144 reg = <0x8000000 0x1000>;
152 reg = <0x8a20000 0x1000>;
155 ranges = <0x0 0x8a20000 0x1000>;
159 reg = <0x120 0x4>;
161 resets = <&crg 0xbc 4>;
163 #size-cells = <0>;
165 usb2_phy1_port0: phy@0 {
166 reg = <0>;
167 #phy-cells = <0>;
168 resets = <&crg 0xbc 8>;
173 #phy-cells = <0>;
174 resets = <&crg 0xbc 9>;
180 reg = <0x124 0x4>;
182 resets = <&crg 0xbc 6>;
184 #size-cells = <0>;
186 usb2_phy2_port0: phy@0 {
187 reg = <0>;
188 #phy-cells = <0>;
189 resets = <&crg 0xbc 10>;
195 reg = <0x850 0x8>;
198 resets = <&crg 0x188 4>;
206 reg = <0x858 0x8>;
209 resets = <&crg 0x188 12>;
212 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
218 reg = <0x8a21000 0x180>;
222 &range 0 8 2 /* GPIO 0 */
223 &range 8 1 0 /* GPIO 1 */
225 &range 13 1 0
227 &range 15 1 0
228 &range 16 5 0 /* GPIO 2 */
233 &range 87 1 0
235 &range 34 3 0
238 &range 41 5 0
242 &range 71 1 0
244 &range 78 1 0
248 &range 88 8 0 /* GPIO 12 */
258 reg = <0x8b00000 0x1000>;
267 reg = <0x8b02000 0x1000>;
276 reg = <0x8b10000 0x1000>;
278 #size-cells = <0>;
287 reg = <0x8b11000 0x1000>;
289 #size-cells = <0>;
298 reg = <0x8b12000 0x1000>;
300 #size-cells = <0>;
309 reg = <0x8b13000 0x1000>;
311 #size-cells = <0>;
320 reg = <0x8b14000 0x1000>;
322 #size-cells = <0>;
331 reg = <0x8b1a000 0x1000>;
334 cs-gpios = <&gpio7 1 0>;
338 #size-cells = <0>;
344 reg = <0x9820000 0x10000>;
349 resets = <&crg 0x9c 4>;
356 reg = <0x9830000 0x10000>;
363 resets = <&crg 0xa0 4>;
370 reg = <0x8b20000 0x1000>;
376 gpio-ranges = <&pmx0 0 0 8>;
384 reg = <0x8b21000 0x1000>;
391 &pmx0 0 8 1
404 reg = <0x8b22000 0x1000>;
410 gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
418 reg = <0x8b23000 0x1000>;
425 &pmx0 0 24 4
437 reg = <0x8b24000 0x1000>;
443 gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
451 reg = <0x8004000 0x1000>;
464 reg = <0x8b26000 0x1000>;
470 gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
478 reg = <0x8b27000 0x1000>;
484 gpio-ranges = <&pmx0 0 46 8>;
492 reg = <0x8b28000 0x1000>;
498 gpio-ranges = <&pmx0 0 54 8>;
506 reg = <0x8b29000 0x1000>;
512 gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
520 reg = <0x8b2a000 0x1000>;
526 gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
534 reg = <0x8b2b000 0x1000>;
540 gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
548 reg = <0x8b2c000 0x1000>;
554 gpio-ranges = <&pmx0 0 88 8>;
562 reg = <0x9840000 0x1000>,
563 <0x984300c 0x4>;
568 resets = <&crg 0xcc 8>,
569 <&crg 0xcc 10>,
570 <&gmacphyrst 0>;
577 reg = <0x9841000 0x1000>,
578 <0x9843010 0x4>;
583 resets = <&crg 0xcc 9>,
584 <&crg 0xcc 11>,
592 reg = <0x8001000 0x1000>;
600 reg = <0x9860000 0x1000>,
601 <0x0 0x2000>,
602 <0x2000000 0x01000000>;
607 bus-range = <0x00 0xff>;
609 ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000>,
610 <0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
614 interrupt-map-mask = <0 0 0 0>;
615 interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
621 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
630 reg = <0x9880000 0x10000>;
636 resets = <&crg 0xb8 12>;
645 reg = <0x9890000 0x10000>;
651 resets = <&crg 0xb8 12>,
652 <&crg 0xb8 16>,
653 <&crg 0xb8 13>;