Lines Matching +full:gpio +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/hi3670-clock.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
27 cpu-map {
58 cpu0: cpu@0 {
59 compatible = "arm,cortex-a53";
61 reg = <0x0 0x0>;
62 enable-method = "psci";
66 compatible = "arm,cortex-a53";
68 reg = <0x0 0x1>;
69 enable-method = "psci";
73 compatible = "arm,cortex-a53";
75 reg = <0x0 0x2>;
76 enable-method = "psci";
80 compatible = "arm,cortex-a53";
82 reg = <0x0 0x3>;
83 enable-method = "psci";
87 compatible = "arm,cortex-a73";
89 reg = <0x0 0x100>;
90 enable-method = "psci";
94 compatible = "arm,cortex-a73";
96 reg = <0x0 0x101>;
97 enable-method = "psci";
101 compatible = "arm,cortex-a73";
103 reg = <0x0 0x102>;
104 enable-method = "psci";
108 compatible = "arm,cortex-a73";
110 reg = <0x0 0x103>;
111 enable-method = "psci";
115 gic: interrupt-controller@e82b0000 {
116 compatible = "arm,gic-400";
117 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
118 <0x0 0xe82b2000 0 0x2000>, /* GICC */
119 <0x0 0xe82b4000 0 0x2000>, /* GICH */
120 <0x0 0xe82b6000 0 0x2000>; /* GICV */
121 #interrupt-cells = <3>;
122 #address-cells = <0>;
125 interrupt-controller;
129 compatible = "arm,armv8-timer";
130 interrupt-parent = <&gic>;
139 clock-frequency = <1920000>;
143 compatible = "simple-bus";
144 #address-cells = <2>;
145 #size-cells = <2>;
149 compatible = "hisilicon,hi3670-crgctrl", "syscon";
150 reg = <0x0 0xfff35000 0x0 0x1000>;
151 #clock-cells = <1>;
155 compatible = "hisilicon,hi3670-reset",
156 "hisilicon,hi3660-reset";
157 #reset-cells = <2>;
158 hisi,rst-syscon = <&crg_ctrl>;
162 compatible = "hisilicon,hi3670-pctrl", "syscon";
163 reg = <0x0 0xe8a09000 0x0 0x1000>;
164 #clock-cells = <1>;
168 compatible = "hisilicon,hi3670-pmuctrl", "syscon";
169 reg = <0x0 0xfff34000 0x0 0x1000>;
170 #clock-cells = <1>;
174 compatible = "hisilicon,hi3670-sctrl", "syscon";
175 reg = <0x0 0xfff0a000 0x0 0x1000>;
176 #clock-cells = <1>;
180 compatible = "hisilicon,hi3670-iomcu", "syscon";
181 reg = <0x0 0xffd7e000 0x0 0x1000>;
182 #clock-cells = <1>;
186 compatible = "hisilicon,hi3670-media1-crg", "syscon";
187 reg = <0x0 0xe87ff000 0x0 0x1000>;
188 #clock-cells = <1>;
192 compatible = "hisilicon,hi3670-media2-crg","syscon";
193 reg = <0x0 0xe8900000 0x0 0x1000>;
194 #clock-cells = <1>;
198 compatible = "hisilicon,hi3660-reset";
199 hisi,rst-syscon = <&iomcu>;
200 #reset-cells = <2>;
205 reg = <0x0 0xfdf02000 0x0 0x1000>;
209 clock-names = "uartclk", "apb_pclk";
210 pinctrl-names = "default";
211 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
217 reg = <0x0 0xfdf00000 0x0 0x1000>;
221 clock-names = "uartclk", "apb_pclk";
227 reg = <0x0 0xfdf03000 0x0 0x1000>;
231 clock-names = "uartclk", "apb_pclk";
232 pinctrl-names = "default";
233 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
239 reg = <0x0 0xffd74000 0x0 0x1000>;
243 clock-names = "uartclk", "apb_pclk";
244 pinctrl-names = "default";
245 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
251 reg = <0x0 0xfdf01000 0x0 0x1000>;
255 clock-names = "uartclk", "apb_pclk";
256 pinctrl-names = "default";
257 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
263 reg = <0x0 0xfdf05000 0x0 0x1000>;
267 clock-names = "uartclk", "apb_pclk";
273 reg = <0x0 0xfff32000 0x0 0x1000>;
277 clock-names = "uartclk", "apb_pclk";
278 pinctrl-names = "default";
279 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
283 gpio0: gpio@e8a0b000 {
285 reg = <0x0 0xe8a0b000 0x0 0x1000>;
287 gpio-controller;
288 #gpio-cells = <2>;
289 gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>;
290 interrupt-controller;
291 #interrupt-cells = <2>;
293 clock-names = "apb_pclk";
296 gpio1: gpio@e8a0c000 {
298 reg = <0x0 0xe8a0c000 0x0 0x1000>;
300 gpio-controller;
301 #gpio-cells = <2>;
302 interrupt-controller;
303 #interrupt-cells = <2>;
305 clock-names = "apb_pclk";
308 gpio2: gpio@e8a0d000 {
310 reg = <0x0 0xe8a0d000 0x0 0x1000>;
312 gpio-controller;
313 #gpio-cells = <2>;
314 gpio-ranges = <&pmx0 1 6 7>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
318 clock-names = "apb_pclk";
321 gpio3: gpio@e8a0e000 {
323 reg = <0x0 0xe8a0e000 0x0 0x1000>;
325 gpio-controller;
326 #gpio-cells = <2>;
327 gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
331 clock-names = "apb_pclk";
334 gpio4: gpio@e8a0f000 {
336 reg = <0x0 0xe8a0f000 0x0 0x1000>;
338 gpio-controller;
339 #gpio-cells = <2>;
340 gpio-ranges = <&pmx0 0 18 8>;
341 interrupt-controller;
342 #interrupt-cells = <2>;
344 clock-names = "apb_pclk";
347 gpio5: gpio@e8a10000 {
349 reg = <0x0 0xe8a10000 0x0 0x1000>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 gpio-ranges = <&pmx0 0 26 8>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
357 clock-names = "apb_pclk";
360 gpio6: gpio@e8a11000 {
362 reg = <0x0 0xe8a11000 0x0 0x1000>;
364 gpio-controller;
365 #gpio-cells = <2>;
366 gpio-ranges = <&pmx0 1 34 7>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
370 clock-names = "apb_pclk";
373 gpio7: gpio@e8a12000 {
375 reg = <0x0 0xe8a12000 0x0 0x1000>;
377 gpio-controller;
378 #gpio-cells = <2>;
379 gpio-ranges = <&pmx0 0 41 8>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
383 clock-names = "apb_pclk";
386 gpio8: gpio@e8a13000 {
388 reg = <0x0 0xe8a13000 0x0 0x1000>;
390 gpio-controller;
391 #gpio-cells = <2>;
392 gpio-ranges = <&pmx0 0 49 8>;
393 interrupt-controller;
394 #interrupt-cells = <2>;
396 clock-names = "apb_pclk";
399 gpio9: gpio@e8a14000 {
401 reg = <0x0 0xe8a14000 0x0 0x1000>;
403 gpio-controller;
404 #gpio-cells = <2>;
405 gpio-ranges = <&pmx0 0 57 8>;
406 interrupt-controller;
407 #interrupt-cells = <2>;
409 clock-names = "apb_pclk";
412 gpio10: gpio@e8a15000 {
414 reg = <0x0 0xe8a15000 0x0 0x1000>;
416 gpio-controller;
417 #gpio-cells = <2>;
418 gpio-ranges = <&pmx0 0 65 8>;
419 interrupt-controller;
420 #interrupt-cells = <2>;
422 clock-names = "apb_pclk";
425 gpio11: gpio@e8a16000 {
427 reg = <0x0 0xe8a16000 0x0 0x1000>;
429 gpio-controller;
430 #gpio-cells = <2>;
431 gpio-ranges = <&pmx0 0 73 8>;
432 interrupt-controller;
433 #interrupt-cells = <2>;
435 clock-names = "apb_pclk";
438 gpio12: gpio@e8a17000 {
440 reg = <0x0 0xe8a17000 0x0 0x1000>;
442 gpio-controller;
443 #gpio-cells = <2>;
444 gpio-ranges = <&pmx0 0 81 1>;
445 interrupt-controller;
446 #interrupt-cells = <2>;
448 clock-names = "apb_pclk";
451 gpio13: gpio@e8a18000 {
453 reg = <0x0 0xe8a18000 0x0 0x1000>;
455 gpio-controller;
456 #gpio-cells = <2>;
457 interrupt-controller;
458 #interrupt-cells = <2>;
460 clock-names = "apb_pclk";
463 gpio14: gpio@e8a19000 {
465 reg = <0x0 0xe8a19000 0x0 0x1000>;
467 gpio-controller;
468 #gpio-cells = <2>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
472 clock-names = "apb_pclk";
475 gpio15: gpio@e8a1a000 {
477 reg = <0x0 0xe8a1a000 0x0 0x1000>;
479 gpio-controller;
480 #gpio-cells = <2>;
481 interrupt-controller;
482 #interrupt-cells = <2>;
484 clock-names = "apb_pclk";
487 gpio16: gpio@e8a1b000 {
489 reg = <0x0 0xe8a1b000 0x0 0x1000>;
491 gpio-controller;
492 #gpio-cells = <2>;
493 gpio-ranges = <&pmx5 0 0 8>;
494 interrupt-controller;
495 #interrupt-cells = <2>;
497 clock-names = "apb_pclk";
500 gpio17: gpio@e8a1c000 {
502 reg = <0x0 0xe8a1c000 0x0 0x1000>;
504 gpio-controller;
505 #gpio-cells = <2>;
506 gpio-ranges = <&pmx5 0 8 2>;
507 interrupt-controller;
508 #interrupt-cells = <2>;
510 clock-names = "apb_pclk";
513 gpio18: gpio@fff28000 {
515 reg = <0x0 0xfff28000 0x0 0x1000>;
517 gpio-controller;
518 #gpio-cells = <2>;
519 gpio-ranges = <&pmx1 4 42 4>;
520 interrupt-controller;
521 #interrupt-cells = <2>;
523 clock-names = "apb_pclk";
526 gpio19: gpio@fff29000 {
528 reg = <0x0 0xfff29000 0x0 0x1000>;
530 gpio-controller;
531 #gpio-cells = <2>;
532 gpio-ranges = <&pmx1 0 61 2>;
533 interrupt-controller;
534 #interrupt-cells = <2>;
536 clock-names = "apb_pclk";
539 gpio20: gpio@e8a1f000 {
541 reg = <0x0 0xe8a1f000 0x0 0x1000>;
543 gpio-controller;
544 #gpio-cells = <2>;
545 gpio-ranges = <&pmx7 0 0 8>;
546 interrupt-controller;
547 #interrupt-cells = <2>;
549 clock-names = "apb_pclk";
552 gpio21: gpio@e8a20000 {
554 reg = <0x0 0xe8a20000 0x0 0x1000>;
556 gpio-controller;
557 #gpio-cells = <2>;
558 gpio-ranges = <&pmx7 0 8 4>;
559 interrupt-controller;
560 #interrupt-cells = <2>;
562 clock-names = "apb_pclk";
565 gpio22: gpio@fff0b000 {
567 reg = <0x0 0xfff0b000 0x0 0x1000>;
569 gpio-controller;
570 #gpio-cells = <2>;
572 gpio-ranges = <&pmx1 2 0 6>;
573 interrupt-controller;
574 #interrupt-cells = <2>;
576 clock-names = "apb_pclk";
579 gpio23: gpio@fff0c000 {
581 reg = <0x0 0xfff0c000 0x0 0x1000>;
583 gpio-controller;
584 #gpio-cells = <2>;
586 gpio-ranges = <&pmx1 0 6 8>;
587 interrupt-controller;
588 #interrupt-cells = <2>;
590 clock-names = "apb_pclk";
593 gpio24: gpio@fff0d000 {
595 reg = <0x0 0xfff0d000 0x0 0x1000>;
597 gpio-controller;
598 #gpio-cells = <2>;
600 gpio-ranges = <&pmx1 0 14 8>;
601 interrupt-controller;
602 #interrupt-cells = <2>;
604 clock-names = "apb_pclk";
607 gpio25: gpio@fff0e000 {
609 reg = <0x0 0xfff0e000 0x0 0x1000>;
611 gpio-controller;
612 #gpio-cells = <2>;
614 gpio-ranges = <&pmx1 0 22 8>;
615 interrupt-controller;
616 #interrupt-cells = <2>;
618 clock-names = "apb_pclk";
621 gpio26: gpio@fff0f000 {
623 reg = <0x0 0xfff0f000 0x0 0x1000>;
625 gpio-controller;
626 #gpio-cells = <2>;
628 gpio-ranges = <&pmx1 0 30 1>;
629 interrupt-controller;
630 #interrupt-cells = <2>;
632 clock-names = "apb_pclk";
635 gpio27: gpio@fff10000 {
637 reg = <0x0 0xfff10000 0x0 0x1000>;
639 gpio-controller;
640 #gpio-cells = <2>;
642 gpio-ranges = <&pmx1 4 31 4>;
643 interrupt-controller;
644 #interrupt-cells = <2>;
646 clock-names = "apb_pclk";
649 gpio28: gpio@fff1d000 {
651 reg = <0x0 0xfff1d000 0x0 0x1000>;
653 gpio-controller;
654 #gpio-cells = <2>;
655 gpio-ranges = <&pmx1 1 35 7>;
656 interrupt-controller;
657 #interrupt-cells = <2>;
659 clock-names = "apb_pclk";
664 compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
665 /* 0: HCI standard */
667 reg = <0x0 0xff3c0000 0x0 0x1000>,
668 <0x0 0xff3e0000 0x0 0x1000>;
669 interrupt-parent = <&gic>;
673 clock-names = "ref_clk", "phy_clk";
674 freq-table-hz = <0 0>,
675 <0 0>;
676 /* offset: 0x84; bit: 12 */
677 resets = <&crg_rst 0x84 12>;
678 reset-names = "rst";
683 compatible = "hisilicon,hi3670-dw-mshc",
684 "hisilicon,hi3660-dw-mshc";
685 reg = <0x0 0xff37f000 0x0 0x1000>;
686 #address-cells = <1>;
687 #size-cells = <0>;
691 clock-names = "ciu", "biu";
692 clock-frequency = <3200000>;
693 resets = <&crg_rst 0x94 18>;
694 reset-names = "reset";
695 hisilicon,peripheral-syscon = <&sctrl>;
696 card-detect-delay = <200>;
702 compatible = "hisilicon,hi3670-dw-mshc",
703 "hisilicon,hi3660-dw-mshc";
704 reg = <0x0 0xfc183000 0x0 0x1000>;
705 #address-cells = <1>;
706 #size-cells = <0>;
710 clock-names = "ciu", "biu";
711 clock-frequency = <3200000>;
712 resets = <&crg_rst 0x94 20>;
713 reset-names = "reset";
714 card-detect-delay = <200>;
720 compatible = "snps,designware-i2c";
721 reg = <0x0 0xffd71000 0x0 0x1000>;
723 #address-cells = <1>;
724 #size-cells = <0>;
725 clock-frequency = <400000>;
727 resets = <&iomcu_rst 0x20 3>;
728 pinctrl-names = "default";
729 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
734 compatible = "snps,designware-i2c";
735 reg = <0x0 0xffd72000 0x0 0x1000>;
737 #address-cells = <1>;
738 #size-cells = <0>;
739 clock-frequency = <400000>;
741 resets = <&iomcu_rst 0x20 4>;
742 pinctrl-names = "default";
743 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
748 compatible = "snps,designware-i2c";
749 reg = <0x0 0xffd73000 0x0 0x1000>;
751 #address-cells = <1>;
752 #size-cells = <0>;
753 clock-frequency = <400000>;
755 resets = <&iomcu_rst 0x20 5>;
756 pinctrl-names = "default";
757 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
762 compatible = "snps,designware-i2c";
763 reg = <0x0 0xfdf0c000 0x0 0x1000>;
765 #address-cells = <1>;
766 #size-cells = <0>;
767 clock-frequency = <400000>;
769 resets = <&crg_rst 0x78 7>;
770 pinctrl-names = "default";
771 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
776 compatible = "snps,designware-i2c";
777 reg = <0x0 0xfdf0d000 0x0 0x1000>;
779 #address-cells = <1>;
780 #size-cells = <0>;
781 clock-frequency = <400000>;
783 resets = <&crg_rst 0x78 27>;
784 pinctrl-names = "default";
785 pinctrl-0 = <&i2c4_pmx_func &i2c4_cfg_func>;