Lines Matching full:crg_ctrl

343 		crg_ctrl: crg_ctrl@fff35000 {  label
352 			hisi,rst-syscon = <&crg_ctrl>;
362 		pmuctrl: crg_ctrl@fff34000 {
407 			clocks = <&crg_ctrl HI3660_OSC32K>,
408 				 <&crg_ctrl HI3660_OSC32K>,
409 				 <&crg_ctrl HI3660_OSC32K>;
420 			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
434 			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
448 			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
462 			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
473 			clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
474 				 <&crg_ctrl HI3660_PCLK>;
487 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
488 				 <&crg_ctrl HI3660_CLK_GATE_UART1>;
501 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
502 				 <&crg_ctrl HI3660_PCLK>;
513 			clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
514 				 <&crg_ctrl HI3660_PCLK>;
527 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
528 				 <&crg_ctrl HI3660_CLK_GATE_UART4>;
541 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
542 				 <&crg_ctrl HI3660_CLK_GATE_UART5>;
553 			clocks = <&crg_ctrl HI3660_CLK_UART6>,
554 				 <&crg_ctrl HI3660_PCLK>;
569 			clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
588 			clocks = <&crg_ctrl HI3660_PCLK>;
601 			clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
614 			clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
627 			clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
640 			clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
653 			clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
666 			clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
679 			clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
692 			clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
705 			clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
718 			clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
731 			clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
744 			clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
757 			clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
770 			clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
783 			clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
796 			clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
808 			clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
820 			clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
833 			clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
846 			clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
859 			clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
872 			clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
978 			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>;
993 			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>;
1029 			clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
1030 				 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
1031 				 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
1032 				 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
1033 				 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
1049 			clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
1050 				<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
1066 			clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
1067 				<&crg_ctrl HI3660_HCLK_GATE_SD>;
1084 			clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
1085 				 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
1097 			clocks = <&crg_ctrl HI3660_OSC32K>,
1098 				 <&crg_ctrl HI3660_OSC32K>;
1106 			clocks = <&crg_ctrl HI3660_OSC32K>,
1107 				 <&crg_ctrl HI3660_OSC32K>;
1170 				hisilicon,pericrg-syscon = <&crg_ctrl>;
1180 			clocks = <&crg_ctrl HI3660_CLK_ABB_USB>,
1181 				 <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
1184 			assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;