Lines Matching +full:0 +full:xf6000000
25 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0 0x0>;
75 reg = <0x0 0x1>;
88 reg = <0x0 0x2>;
101 reg = <0x0 0x3>;
114 reg = <0x0 0x100>;
128 reg = <0x0 0x101>;
141 reg = <0x0 0x102>;
154 reg = <0x0 0x103>;
167 CPU_SLEEP_0: cpu-sleep-0 {
170 arm,psci-suspend-param = <0x0010000>;
175 CLUSTER_SLEEP_0: cluster-sleep-0 {
178 arm,psci-suspend-param = <0x1010000>;
188 arm,psci-suspend-param = <0x0010000>;
197 arm,psci-suspend-param = <0x1010000>;
217 cluster0_opp: opp-table-0 {
289 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
290 <0x0 0xe82b2000 0 0x2000>, /* GICC */
291 <0x0 0xe82b4000 0 0x2000>, /* GICH */
292 <0x0 0xe82b6000 0 0x2000>; /* GICV */
293 #address-cells = <0>;
345 reg = <0x0 0xfff35000 0x0 0x1000>;
358 reg = <0x0 0xe8a09000 0x0 0x2000>;
364 reg = <0x0 0xfff34000 0x0 0x1000>;
370 reg = <0x0 0xfff0a000 0x0 0x1000>;
376 reg = <0x0 0xffd7e000 0x0 0x1000>;
389 reg = <0x0 0xe896b000 0x0 0x1000>;
397 reg = <0x0 0xe896b500 0x0 0x0100>;
399 mboxes = <&mailbox 13 3 0>;
404 reg = <0x0 0xfff14000 0x0 0x1000>;
415 reg = <0x0 0xffd71000 0x0 0x1000>;
418 #size-cells = <0>;
421 resets = <&iomcu_rst 0x20 3>;
423 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
429 reg = <0x0 0xffd72000 0x0 0x1000>;
432 #size-cells = <0>;
435 resets = <&iomcu_rst 0x20 4>;
437 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
443 reg = <0x0 0xfdf0c000 0x0 0x1000>;
446 #size-cells = <0>;
449 resets = <&crg_rst 0x78 7>;
451 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
457 reg = <0x0 0xfdf0b000 0x0 0x1000>;
460 #size-cells = <0>;
463 resets = <&crg_rst 0x60 14>;
465 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
471 reg = <0x0 0xfdf02000 0x0 0x1000>;
477 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
483 reg = <0x0 0xfdf00000 0x0 0x1000>;
491 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
497 reg = <0x0 0xfdf03000 0x0 0x1000>;
505 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
511 reg = <0x0 0xffd74000 0x0 0x1000>;
517 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
523 reg = <0x0 0xfdf01000 0x0 0x1000>;
531 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
537 reg = <0x0 0xfdf05000 0x0 0x1000>;
545 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
551 reg = <0x0 0xfff32000 0x0 0x1000>;
557 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
563 reg = <0x0 0xfdf30000 0x0 0x1000>;
567 dma-channel-mask = <0xfffe>;
576 reg = <0x0 0xe804b000 0x0 0x1000>;
586 reg = <0x0 0Xfff04000 0x0 0x1000>;
594 reg = <0 0xe8a0b000 0 0x1000>;
598 gpio-ranges = <&pmx0 1 0 7>;
607 reg = <0 0xe8a0c000 0 0x1000>;
620 reg = <0 0xe8a0d000 0 0x1000>;
624 gpio-ranges = <&pmx0 0 14 8>;
633 reg = <0 0xe8a0e000 0 0x1000>;
637 gpio-ranges = <&pmx0 0 22 8>;
646 reg = <0 0xe8a0f000 0 0x1000>;
650 gpio-ranges = <&pmx0 0 30 8>;
659 reg = <0 0xe8a10000 0 0x1000>;
663 gpio-ranges = <&pmx0 0 38 8>;
672 reg = <0 0xe8a11000 0 0x1000>;
676 gpio-ranges = <&pmx0 0 46 8>;
685 reg = <0 0xe8a12000 0 0x1000>;
689 gpio-ranges = <&pmx0 0 54 8>;
698 reg = <0 0xe8a13000 0 0x1000>;
702 gpio-ranges = <&pmx0 0 62 8>;
711 reg = <0 0xe8a14000 0 0x1000>;
715 gpio-ranges = <&pmx0 0 70 8>;
724 reg = <0 0xe8a15000 0 0x1000>;
728 gpio-ranges = <&pmx0 0 78 8>;
737 reg = <0 0xe8a16000 0 0x1000>;
741 gpio-ranges = <&pmx0 0 86 8>;
750 reg = <0 0xe8a17000 0 0x1000>;
754 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
763 reg = <0 0xe8a18000 0 0x1000>;
767 gpio-ranges = <&pmx0 0 102 8>;
776 reg = <0 0xe8a19000 0 0x1000>;
780 gpio-ranges = <&pmx0 0 110 8>;
789 reg = <0 0xe8a1a000 0 0x1000>;
793 gpio-ranges = <&pmx0 0 118 6>;
802 reg = <0 0xe8a1b000 0 0x1000>;
814 reg = <0 0xe8a1c000 0 0x1000>;
826 reg = <0 0xff3b4000 0 0x1000>;
830 gpio-ranges = <&pmx2 0 0 8>;
839 reg = <0 0xff3b5000 0 0x1000>;
843 gpio-ranges = <&pmx2 0 8 4>;
852 reg = <0 0xe8a1f000 0 0x1000>;
856 gpio-ranges = <&pmx1 0 0 6>;
865 reg = <0 0xe8a20000 0 0x1000>;
871 gpio-ranges = <&pmx3 0 0 6>;
878 reg = <0 0xfff0b000 0 0x1000>;
883 gpio-ranges = <&pmx4 2 0 6>;
892 reg = <0 0xfff0c000 0 0x1000>;
897 gpio-ranges = <&pmx4 0 6 7>;
906 reg = <0 0xfff0d000 0 0x1000>;
911 gpio-ranges = <&pmx4 0 13 8>;
920 reg = <0 0xfff0e000 0 0x1000>;
925 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
934 reg = <0 0xfff0f000 0 0x1000>;
939 gpio-ranges = <&pmx4 0 28 8>;
948 reg = <0 0xfff10000 0 0x1000>;
953 gpio-ranges = <&pmx4 0 36 6>;
962 reg = <0 0xfff1d000 0 0x1000>;
974 reg = <0x0 0xffd68000 0x0 0x1000>;
976 #size-cells = <0>;
981 pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>;
983 cs-gpios = <&gpio27 2 0>;
989 reg = <0x0 0xff3b3000 0x0 0x1000>;
991 #size-cells = <0>;
996 pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>;
998 cs-gpios = <&gpio18 5 0>;
1004 reg = <0x0 0xf4000000 0x0 0x1000>,
1005 <0x0 0xff3fe000 0x0 0x1000>,
1006 <0x0 0xf3f20000 0x0 0x40000>,
1007 <0x0 0xf5000000 0x0 0x2000>;
1009 bus-range = <0x0 0xff>;
1013 ranges = <0x02000000 0x0 0x00000000
1014 0x0 0xf6000000
1015 0x0 0x02000000>;
1018 interrupts = <0 283 4>;
1020 interrupt-map-mask = <0xf800 0 0 7>;
1021 interrupt-map = <0x0 0 0 1
1023 <0x0 0 0 2
1025 <0x0 0 0 3
1027 <0x0 0 0 4
1037 reset-gpios = <&gpio11 1 0 >;
1043 /* 0: HCI standard */
1045 reg = <0x0 0xff3b0000 0x0 0x1000>,
1046 <0x0 0xff3b1000 0x0 0x1000>;
1052 freq-table-hz = <0 0>,
1053 <0 0>;
1054 /* offset: 0x84; bit: 12 */
1055 resets = <&crg_rst 0x84 12>;
1062 reg = <0x0 0xff37f000 0x0 0x1000>;
1064 #size-cells = <0>;
1070 resets = <&crg_rst 0x94 18>;
1080 reg = <0x0 0xff3ff000 0x0 0x1000>;
1081 #address-cells = <0x1>;
1082 #size-cells = <0x0>;
1087 resets = <&crg_rst 0x94 20>;
1095 reg = <0x0 0xe8a06000 0x0 0x1000>;
1104 reg = <0x0 0xe8a07000 0x0 0x1000>;
1113 reg = <0x0 0xfff30000 0x0 0x1000>;
1165 reg = <0x0 0xff200000 0x0 0x1000>;
1169 #phy-cells = <0>;
1172 hisilicon,eye-diagram-param = <0x22466e4>;
1178 reg = <0x0 0xff100000 0x0 0x100000>;
1187 resets = <&crg_rst 0x90 8>,
1188 <&crg_rst 0x90 7>,
1189 <&crg_rst 0x90 6>,
1190 <&crg_rst 0x90 5>;
1192 interrupts = <0 159 4>, <0 161 4>;