Lines Matching +full:psci +full:- +full:0
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright 2021-2024 NXP
7 * Andra-Teodora Ilie <andra.ilie@nxp.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <0x02>;
16 #size-cells = <0x02>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cpu-map {
60 cpu0: cpu@0 {
62 compatible = "arm,cortex-a53";
63 reg = <0x0>;
64 enable-method = "psci";
65 clocks = <&dfs 0>;
70 compatible = "arm,cortex-a53";
71 reg = <0x1>;
72 enable-method = "psci";
73 clocks = <&dfs 0>;
78 compatible = "arm,cortex-a53";
79 reg = <0x2>;
80 enable-method = "psci";
81 clocks = <&dfs 0>;
86 compatible = "arm,cortex-a53";
87 reg = <0x3>;
88 enable-method = "psci";
89 clocks = <&dfs 0>;
94 compatible = "arm,cortex-a53";
95 reg = <0x100>;
96 enable-method = "psci";
97 clocks = <&dfs 0>;
102 compatible = "arm,cortex-a53";
103 reg = <0x101>;
104 enable-method = "psci";
105 clocks = <&dfs 0>;
110 compatible = "arm,cortex-a53";
111 reg = <0x102>;
112 enable-method = "psci";
113 clocks = <&dfs 0>;
118 compatible = "arm,cortex-a53";
119 reg = <0x103>;
120 enable-method = "psci";
121 clocks = <&dfs 0>;
127 compatible = "arm,scmi-smc";
129 arm,smc-id = <0xc20000fe>;
130 #address-cells = <1>;
131 #size-cells = <0>;
134 reg = <0x13>;
135 #clock-cells = <1>;
139 reg = <0x14>;
140 #clock-cells = <1>;
144 psci: psci { label
145 compatible = "arm,psci-1.0";
152 compatible = "arm,cortex-a53-pmu";
156 reserved-memory {
157 #address-cells = <2>;
158 #size-cells = <2>;
162 compatible = "arm,scmi-shmem";
163 reg = <0x0 0xd0000000 0x0 0x80>;
164 no-map;
168 soc@0 {
169 compatible = "simple-bus";
170 #address-cells = <1>;
171 #size-cells = <1>;
172 ranges = <0 0 0 0x80000000>;
175 compatible = "nxp,s32g2-siul2-pinctrl";
176 /* MSCR0-MSCR101 registers on siul2_0 */
177 reg = <0x4009c240 0x198>,
178 /* MSCR112-MSCR122 registers on siul2_1 */
179 <0x44010400 0x2c>,
180 /* MSCR144-MSCR190 registers on siul2_1 */
181 <0x44010480 0xbc>,
182 /* IMCR0-IMCR83 registers on siul2_0 */
183 <0x4009ca40 0x150>,
184 /* IMCR119-IMCR397 registers on siul2_1 */
185 <0x44010c1c 0x45c>,
186 /* IMCR430-IMCR495 registers on siul2_1 */
187 <0x440110f8 0x108>;
189 jtag_pins: jtag-pins {
190 jtag-grp0 {
191 pinmux = <0x0>;
192 input-enable;
193 bias-pull-up;
194 slew-rate = <166>;
197 jtag-grp1 {
198 pinmux = <0x11>;
199 slew-rate = <166>;
202 jtag-grp2 {
203 pinmux = <0x40>;
204 input-enable;
205 bias-pull-down;
206 slew-rate = <166>;
209 jtag-grp3 {
210 pinmux = <0x23c0>,
211 <0x23d0>,
212 <0x2320>;
215 jtag-grp4 {
216 pinmux = <0x51>;
217 input-enable;
218 bias-pull-up;
219 slew-rate = <166>;
225 compatible = "nxp,s32g3-linflexuart",
226 "fsl,s32v234-linflexuart";
227 reg = <0x401c8000 0x3000>;
233 compatible = "nxp,s32g3-linflexuart",
234 "fsl,s32v234-linflexuart";
235 reg = <0x401cc000 0x3000>;
241 compatible = "nxp,s32g3-linflexuart",
242 "fsl,s32v234-linflexuart";
243 reg = <0x402bc000 0x3000>;
249 compatible = "nxp,s32g3-usdhc",
250 "nxp,s32g2-usdhc";
251 reg = <0x402f0000 0x1000>;
256 clock-names = "ipg", "ahb", "per";
260 gic: interrupt-controller@50800000 {
261 compatible = "arm,gic-v3";
262 #interrupt-cells = <3>;
263 interrupt-controller;
264 reg = <0x50800000 0x10000>,
265 <0x50900000 0x200000>,
266 <0x50400000 0x2000>,
267 <0x50410000 0x2000>,
268 <0x50420000 0x2000>;
274 compatible = "arm,armv8-timer";
275 interrupt-parent = <&gic>;
276 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */
279 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */
280 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */
281 arm,no-tick-in-suspend;