Lines Matching +full:0 +full:x4009c240
15 #address-cells = <0x02>;
16 #size-cells = <0x02>;
20 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0x0>;
65 clocks = <&dfs 0>;
71 reg = <0x1>;
73 clocks = <&dfs 0>;
79 reg = <0x2>;
81 clocks = <&dfs 0>;
87 reg = <0x3>;
89 clocks = <&dfs 0>;
95 reg = <0x100>;
97 clocks = <&dfs 0>;
103 reg = <0x101>;
105 clocks = <&dfs 0>;
111 reg = <0x102>;
113 clocks = <&dfs 0>;
119 reg = <0x103>;
121 clocks = <&dfs 0>;
129 arm,smc-id = <0xc20000fe>;
131 #size-cells = <0>;
134 reg = <0x13>;
139 reg = <0x14>;
163 reg = <0x0 0xd0000000 0x0 0x80>;
168 soc@0 {
172 ranges = <0 0 0 0x80000000>;
177 reg = <0x4009c240 0x198>,
179 <0x44010400 0x2c>,
181 <0x44010480 0xbc>,
183 <0x4009ca40 0x150>,
185 <0x44010c1c 0x45c>,
187 <0x440110f8 0x108>;
191 pinmux = <0x0>;
198 pinmux = <0x11>;
203 pinmux = <0x40>;
210 pinmux = <0x23c0>,
211 <0x23d0>,
212 <0x2320>;
216 pinmux = <0x51>;
227 reg = <0x401c8000 0x3000>;
235 reg = <0x401cc000 0x3000>;
243 reg = <0x402bc000 0x3000>;
251 reg = <0x402f0000 0x1000>;
264 reg = <0x50800000 0x10000>,
265 <0x50900000 0x200000>,
266 <0x50400000 0x2000>,
267 <0x50410000 0x2000>,
268 <0x50420000 0x2000>;