Lines Matching +full:0 +full:x44450000
48 #size-cells = <0>;
55 arm,psci-suspend-param = <0x0010033>;
64 A55_0: cpu@0 {
67 reg = <0x0>;
76 reg = <0x100>;
86 #clock-cells = <0>;
93 #clock-cells = <0>;
100 #clock-cells = <0>;
128 reg = <0 0x48000000 0 0x10000>,
129 <0 0x48040000 0 0xc0000>;
141 thermal-sensors = <&tmu 0>;
186 soc@0 {
190 ranges = <0x0 0x0 0x0 0x80000000>,
191 <0x28000000 0x0 0x28000000 0x10000000>;
195 reg = <0x44000000 0x800000>;
202 reg = <0x44000000 0x200000>;
205 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, // 0: Reserved
242 reg = <0x44210000 0x1000>;
247 reg = <0x44230000 0x10000>;
256 reg = <0x44290000 0x30000>;
265 reg = <0x442d0000 0x10000>;
274 reg = <0x442e0000 0x10000>;
283 reg = <0x44310000 0x1000>;
291 reg = <0x44320000 0x10000>;
299 reg = <0x44330000 0x10000>;
302 #size-cells = <0>;
312 reg = <0x44340000 0x10000>;
314 #size-cells = <0>;
324 reg = <0x44350000 0x10000>;
326 #size-cells = <0>;
336 #size-cells = <0>;
338 reg = <0x44360000 0x10000>;
348 #size-cells = <0>;
350 reg = <0x44370000 0x10000>;
360 reg = <0x44380000 0x1000>;
364 dmas = <&edma1 17 0 1>, <&edma1 16 0 0>;
371 reg = <0x44390000 0x1000>;
375 dmas = <&edma1 19 0 1>, <&edma1 18 0 0>;
382 reg = <0x443a0000 0x10000>;
390 fsl,clk-source = /bits/ 8 <0>;
391 fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>;
397 reg = <0x443b0000 0x10000>;
403 dmas = <&edma1 22 0 1>, <&edma1 21 0 0>;
410 reg = <0x443c0000 0x10000>;
416 reg = <0x44440000 0x10000>;
432 reg = <0x44450000 0x10000>;
443 reg = <0x44460000 0x10000>;
450 reg = <0x44461800 0x400>, <0x44464800 0x400>;
451 #power-domain-cells = <0>;
458 reg = <0x44462400 0x400>, <0x44465800 0x400>;
459 #power-domain-cells = <0>;
467 reg = <0x44480000 0x2000>;
473 reg = <0x44482000 0x1000>;
477 fsl,tmu-range = <0x800000da 0x800000e9
478 0x80000102 0x8000012a
479 0x80000166 0x800001a7
480 0x800001b6>;
481 fsl,tmu-calibration = <0x00000000 0x0000000e
482 0x00000001 0x00000029
483 0x00000002 0x00000056
484 0x00000003 0x000000a2
485 0x00000004 0x00000116
486 0x00000005 0x00000195
487 0x00000006 0x000001b2>;
493 reg = <0x44520000 0x10000>;
502 dmas = <&edma1 29 0 5>;
509 reg = <0x44530000 0x10000>;
523 reg = <0x42000000 0x800000>;
530 reg = <0x42000000 0x210000>;
603 reg = <0x42420000 0x1000>;
608 reg = <0x42440000 0x10000>;
617 reg = <0x42490000 0x10000>;
626 reg = <0x424a0000 0x10000>;
635 reg = <0x424b0000 0x10000>;
644 reg = <0x424e0000 0x1000>;
652 reg = <0x424f0000 0x10000>;
660 reg = <0x42500000 0x10000>;
668 reg = <0x42510000 0x10000>;
676 reg = <0x42520000 0x10000>;
679 #size-cells = <0>;
689 reg = <0x42530000 0x10000>;
691 #size-cells = <0>;
701 reg = <0x42540000 0x10000>;
703 #size-cells = <0>;
713 #size-cells = <0>;
715 reg = <0x42550000 0x10000>;
725 #size-cells = <0>;
727 reg = <0x42560000 0x10000>;
737 reg = <0x42570000 0x1000>;
741 dmas = <&edma2 18 0 1>, <&edma2 17 0 0>;
748 reg = <0x42580000 0x1000>;
752 dmas = <&edma2 20 0 1>, <&edma2 19 0 0>;
759 reg = <0x42590000 0x1000>;
763 dmas = <&edma2 22 0 1>, <&edma2 21 0 0>;
770 reg = <0x425a0000 0x1000>;
774 dmas = <&edma2 24 0 1>, <&edma2 23 0 0>;
781 reg = <0x425b0000 0x10000>;
789 fsl,clk-source = /bits/ 8 <0>;
790 fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>;
796 reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
799 #size-cells = <0>;
811 reg = <0x42650000 0x10000>;
817 dmas = <&edma2 59 0 1>, <&edma2 58 0 0>;
824 reg = <0x42660000 0x10000>;
830 dmas = <&edma2 61 0 1>, <&edma2 60 0 0>;
837 reg = <0x42680000 0x800>,
838 <0x42680800 0x400>,
839 <0x42680c00 0x080>,
840 <0x42680e00 0x080>;
849 dmas = <&edma2 65 0 1>, <&edma2 66 0 0>;
856 reg = <0x42690000 0x1000>;
860 dmas = <&edma2 88 0 1>, <&edma2 87 0 0>;
867 reg = <0x426a0000 0x1000>;
871 dmas = <&edma2 90 0 1>, <&edma2 89 0 0>;
878 reg = <0x426b0000 0x10000>;
880 #size-cells = <0>;
890 reg = <0x426c0000 0x10000>;
892 #size-cells = <0>;
902 reg = <0x426d0000 0x10000>;
904 #size-cells = <0>;
914 reg = <0x426e0000 0x10000>;
916 #size-cells = <0>;
926 #size-cells = <0>;
928 reg = <0x426f0000 0x10000>;
938 #size-cells = <0>;
940 reg = <0x42700000 0x10000>;
950 #size-cells = <0>;
952 reg = <0x42710000 0x10000>;
962 #size-cells = <0>;
964 reg = <0x42720000 0x10000>;
976 reg = <0x42800000 0x800000>;
983 reg = <0x42850000 0x10000>;
997 reg = <0x42860000 0x10000>;
1011 reg = <0x42890000 0x10000>;
1032 fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>;
1038 reg = <0x428a0000 0x10000>;
1053 intf_mode = <&wakeupmix_gpr 0x28>;
1054 snps,clk-csr = <0>;
1060 reg = <0x428b0000 0x10000>;
1075 reg = <0x43810000 0x1000>;
1085 gpio-ranges = <&iomuxc 0 4 30>;
1090 reg = <0x43820000 0x1000>;
1100 gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
1101 <&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
1106 reg = <0x43830000 0x1000>;
1116 gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
1121 reg = <0x47400000 0x1000>;
1131 gpio-ranges = <&iomuxc 0 92 16>;
1136 reg = <0x47510000 0x10000>;
1143 reg = <0x47520000 0x10000>;
1152 reg = <0x4ac10000 0x10000>;
1172 reg = <0x4e300dc0 0x200>;