Lines Matching +full:imx7ulp +full:- +full:usdhc
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8ulp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/imx8ulp-power.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8ulp-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
34 #address-cells = <2>;
35 #size-cells = <0>;
39 compatible = "arm,cortex-a35";
41 enable-method = "psci";
42 next-level-cache = <&A35_L2>;
43 cpu-idle-states = <&cpu_sleep>;
48 compatible = "arm,cortex-a35";
50 enable-method = "psci";
51 next-level-cache = <&A35_L2>;
52 cpu-idle-states = <&cpu_sleep>;
55 A35_L2: l2-cache0 {
57 cache-level = <2>;
58 cache-unified;
61 idle-states {
62 entry-method = "psci";
64 cpu_sleep: cpu-sleep {
65 compatible = "arm,idle-state";
66 arm,psci-suspend-param = <0x0>;
67 local-timer-stop;
68 entry-latency-us = <1000>;
69 exit-latency-us = <700>;
70 min-residency-us = <2700>;
75 gic: interrupt-controller@2d400000 {
76 compatible = "arm,gic-v3";
79 #interrupt-cells = <3>;
80 interrupt-controller;
85 compatible = "arm,cortex-a35-pmu";
86 interrupt-parent = <&gic>;
89 interrupt-affinity = <&A35_0>, <&A35_1>;
93 compatible = "arm,psci-1.0";
97 thermal-zones {
98 cpu-thermal {
99 polling-delay-passive = <250>;
100 polling-delay = <2000>;
101 thermal-sensors = <&scmi_sensor 0>;
120 compatible = "arm,armv8-timer";
122 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
127 frosc: clock-frosc {
128 compatible = "fixed-clock";
129 clock-frequency = <192000000>;
130 clock-output-names = "frosc";
131 #clock-cells = <0>;
134 lposc: clock-lposc {
135 compatible = "fixed-clock";
136 clock-frequency = <1000000>;
137 clock-output-names = "lposc";
138 #clock-cells = <0>;
141 rosc: clock-rosc {
142 compatible = "fixed-clock";
143 clock-frequency = <32768>;
144 clock-output-names = "rosc";
145 #clock-cells = <0>;
148 sosc: clock-sosc {
149 compatible = "fixed-clock";
150 clock-frequency = <24000000>;
151 clock-output-names = "sosc";
152 #clock-cells = <0>;
156 compatible = "mmio-sram";
159 #address-cells = <1>;
160 #size-cells = <1>;
163 scmi_buf: scmi-sram-section@0 {
164 compatible = "arm,scmi-shmem";
171 compatible = "arm,scmi-smc";
172 arm,smc-id = <0xc20000fe>;
173 #address-cells = <1>;
174 #size-cells = <0>;
179 #power-domain-cells = <1>;
184 #thermal-sensor-cells = <1>;
189 cm33: remoteproc-cm33 {
190 compatible = "fsl,imx8ulp-cm33";
195 compatible = "simple-bus";
196 #address-cells = <1>;
197 #size-cells = <1>;
202 compatible = "fsl,imx8ulp-mu-s4";
205 #mbox-cells = <2>;
209 compatible = "simple-bus";
211 #address-cells = <1>;
212 #size-cells = <1>;
216 compatible = "fsl,imx8ulp-mu";
219 #mbox-cells = <2>;
224 compatible = "fsl,imx8ulp-mu";
228 #mbox-cells = <2>;
233 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
237 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
238 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
239 timeout-sec = <40>;
242 cgc1: clock-controller@292c0000 {
243 compatible = "fsl,imx8ulp-cgc1";
245 #clock-cells = <1>;
248 pcc3: clock-controller@292d0000 {
249 compatible = "fsl,imx8ulp-pcc3";
251 #clock-cells = <1>;
252 #reset-cells = <1>;
256 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
261 clock-names = "ipg", "per";
266 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
271 clock-names = "per", "ipg";
272 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
273 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
274 assigned-clock-rates = <48000000>;
279 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
284 clock-names = "per", "ipg";
285 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
286 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
287 assigned-clock-rates = <48000000>;
292 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
296 clock-names = "ipg";
301 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
305 clock-names = "ipg";
310 #address-cells = <1>;
311 #size-cells = <0>;
312 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
317 clock-names = "per", "ipg";
318 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
319 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
320 assigned-clock-rates = <48000000>;
325 #address-cells = <1>;
326 #size-cells = <0>;
327 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
332 clock-names = "per", "ipg";
333 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
334 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
335 assigned-clock-rates = <48000000>;
341 compatible = "simple-bus";
343 #address-cells = <1>;
344 #size-cells = <1>;
347 pcc4: clock-controller@29800000 {
348 compatible = "fsl,imx8ulp-pcc4";
350 #clock-cells = <1>;
351 #reset-cells = <1>;
355 compatible = "nxp,imx8mm-fspi";
357 reg-names = "fspi_base", "fspi_mmap";
358 #address-cells = <1>;
359 #size-cells = <0>;
363 clock-names = "fspi_en", "fspi";
364 assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
365 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
370 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
375 clock-names = "per", "ipg";
376 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
377 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
378 assigned-clock-rates = <48000000>;
383 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
388 clock-names = "per", "ipg";
389 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
390 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
391 assigned-clock-rates = <48000000>;
396 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
400 clock-names = "ipg";
405 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
409 clock-names = "ipg";
414 compatible = "fsl,imx8ulp-iomuxc1";
419 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
425 clock-names = "ipg", "ahb", "per";
426 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
427 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>,
429 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>;
430 assigned-clock-rates = <389283840>, <389283840>;
431 fsl,tuning-start-tap = <20>;
432 fsl,tuning-step = <2>;
433 bus-width = <4>;
438 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
444 clock-names = "ipg", "ahb", "per";
445 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
446 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
448 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
449 assigned-clock-rates = <194641920>, <194641920>;
450 fsl,tuning-start-tap = <20>;
451 fsl,tuning-step = <2>;
452 bus-width = <4>;
457 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
463 clock-names = "ipg", "ahb", "per";
464 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
465 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
467 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
468 assigned-clock-rates = <194641920>, <194641920>;
469 fsl,tuning-start-tap = <20>;
470 fsl,tuning-step = <2>;
471 bus-width = <4>;
476 compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
479 interrupt-names = "int0";
480 fsl,num-tx-queues = <1>;
481 fsl,num-rx-queues = <1>;
487 compatible = "fsl,imx8ulp-gpio";
489 gpio-controller;
490 #gpio-cells = <2>;
493 interrupt-controller;
494 #interrupt-cells = <2>;
497 clock-names = "gpio", "port";
498 gpio-ranges = <&iomuxc1 0 32 24>;
502 compatible = "fsl,imx8ulp-gpio";
504 gpio-controller;
505 #gpio-cells = <2>;
508 interrupt-controller;
509 #interrupt-cells = <2>;
512 clock-names = "gpio", "port";
513 gpio-ranges = <&iomuxc1 0 64 32>;
517 compatible = "simple-bus";
519 #address-cells = <1>;
520 #size-cells = <1>;
523 cgc2: clock-controller@2da60000 {
524 compatible = "fsl,imx8ulp-cgc2";
526 #clock-cells = <1>;
529 pcc5: clock-controller@2da70000 {
530 compatible = "fsl,imx8ulp-pcc5";
532 #clock-cells = <1>;
533 #reset-cells = <1>;
538 compatible = "fsl,imx8ulp-gpio";
540 gpio-controller;
541 #gpio-cells = <2>;
544 interrupt-controller;
545 #interrupt-cells = <2>;
548 clock-names = "gpio", "port";
549 gpio-ranges = <&iomuxc1 0 0 24>;