Lines Matching +full:imx8 +full:- +full:lpcg
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
27 vpu-core0 = &vpu_core0;
28 vpu-core1 = &vpu_core1;
29 vpu-core2 = &vpu_core2;
33 #address-cells = <2>;
34 #size-cells = <0>;
36 cpu-map {
64 compatible = "arm,cortex-a53";
67 enable-method = "psci";
68 i-cache-size = <0x8000>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <256>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
74 next-level-cache = <&A53_L2>;
75 operating-points-v2 = <&a53_opp_table>;
76 #cooling-cells = <2>;
81 compatible = "arm,cortex-a53";
84 enable-method = "psci";
85 i-cache-size = <0x8000>;
86 i-cache-line-size = <64>;
87 i-cache-sets = <256>;
88 d-cache-size = <0x8000>;
89 d-cache-line-size = <64>;
90 d-cache-sets = <128>;
91 next-level-cache = <&A53_L2>;
92 operating-points-v2 = <&a53_opp_table>;
93 #cooling-cells = <2>;
98 compatible = "arm,cortex-a53";
101 enable-method = "psci";
102 i-cache-size = <0x8000>;
103 i-cache-line-size = <64>;
104 i-cache-sets = <256>;
105 d-cache-size = <0x8000>;
106 d-cache-line-size = <64>;
107 d-cache-sets = <128>;
108 next-level-cache = <&A53_L2>;
109 operating-points-v2 = <&a53_opp_table>;
110 #cooling-cells = <2>;
115 compatible = "arm,cortex-a53";
118 enable-method = "psci";
119 i-cache-size = <0x8000>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <256>;
122 d-cache-size = <0x8000>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&A53_L2>;
126 operating-points-v2 = <&a53_opp_table>;
127 #cooling-cells = <2>;
132 compatible = "arm,cortex-a72";
135 enable-method = "psci";
136 i-cache-size = <0xC000>;
137 i-cache-line-size = <64>;
138 i-cache-sets = <256>;
139 d-cache-size = <0x8000>;
140 d-cache-line-size = <64>;
141 d-cache-sets = <256>;
142 next-level-cache = <&A72_L2>;
143 operating-points-v2 = <&a72_opp_table>;
144 #cooling-cells = <2>;
149 compatible = "arm,cortex-a72";
152 enable-method = "psci";
153 next-level-cache = <&A72_L2>;
154 operating-points-v2 = <&a72_opp_table>;
155 #cooling-cells = <2>;
158 A53_L2: l2-cache0 {
160 cache-level = <2>;
161 cache-unified;
162 cache-size = <0x100000>;
163 cache-line-size = <64>;
164 cache-sets = <1024>;
167 A72_L2: l2-cache1 {
169 cache-level = <2>;
170 cache-unified;
171 cache-size = <0x100000>;
172 cache-line-size = <64>;
173 cache-sets = <1024>;
177 a53_opp_table: opp-table-0 {
178 compatible = "operating-points-v2";
179 opp-shared;
181 opp-600000000 {
182 opp-hz = /bits/ 64 <600000000>;
183 opp-microvolt = <900000>;
184 clock-latency-ns = <150000>;
187 opp-896000000 {
188 opp-hz = /bits/ 64 <896000000>;
189 opp-microvolt = <1000000>;
190 clock-latency-ns = <150000>;
193 opp-1104000000 {
194 opp-hz = /bits/ 64 <1104000000>;
195 opp-microvolt = <1100000>;
196 clock-latency-ns = <150000>;
199 opp-1200000000 {
200 opp-hz = /bits/ 64 <1200000000>;
201 opp-microvolt = <1100000>;
202 clock-latency-ns = <150000>;
203 opp-suspend;
207 a72_opp_table: opp-table-1 {
208 compatible = "operating-points-v2";
209 opp-shared;
211 opp-600000000 {
212 opp-hz = /bits/ 64 <600000000>;
213 opp-microvolt = <1000000>;
214 clock-latency-ns = <150000>;
217 opp-1056000000 {
218 opp-hz = /bits/ 64 <1056000000>;
219 opp-microvolt = <1000000>;
220 clock-latency-ns = <150000>;
223 opp-1296000000 {
224 opp-hz = /bits/ 64 <1296000000>;
225 opp-microvolt = <1100000>;
226 clock-latency-ns = <150000>;
229 opp-1596000000 {
230 opp-hz = /bits/ 64 <1596000000>;
231 opp-microvolt = <1100000>;
232 clock-latency-ns = <150000>;
233 opp-suspend;
237 gic: interrupt-controller@51a00000 {
238 compatible = "arm,gic-v3";
244 #interrupt-cells = <3>;
245 interrupt-controller;
247 interrupt-parent = <&gic>;
251 compatible = "arm,armv8-pmuv3";
256 compatible = "arm,psci-1.0";
261 compatible = "arm,armv8-timer";
263 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
268 system-controller {
269 compatible = "fsl,imx-scu";
270 mbox-names = "tx0",
277 pd: power-controller {
278 compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
279 #power-domain-cells = <1>;
282 clk: clock-controller {
283 compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
284 #clock-cells = <2>;
288 compatible = "fsl,imx8qm-iomuxc";
292 compatible = "fsl,imx8qxp-sc-rtc";
295 tsens: thermal-sensor {
296 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
297 #thermal-sensor-cells = <1>;
301 thermal-zones {
302 cpu0-thermal {
303 polling-delay-passive = <250>;
304 polling-delay = <2000>;
305 thermal-sensors = <&tsens IMX_SC_R_A53>;
321 cooling-maps {
324 cooling-device =
333 cpu1-thermal {
334 polling-delay-passive = <250>;
335 polling-delay = <2000>;
336 thermal-sensors = <&tsens IMX_SC_R_A72>;
352 cooling-maps {
355 cooling-device =
362 gpu0-thermal {
363 polling-delay-passive = <250>;
364 polling-delay = <2000>;
365 thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>;
382 gpu1-thermal {
383 polling-delay-passive = <250>;
384 polling-delay = <2000>;
385 thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>;
402 drc0-thermal {
403 polling-delay-passive = <250>;
404 polling-delay = <2000>;
405 thermal-sensors = <&tsens IMX_SC_R_DRC_0>;
424 #include "imx8-ss-vpu.dtsi"
425 #include "imx8-ss-img.dtsi"
426 #include "imx8-ss-dma.dtsi"
427 #include "imx8-ss-conn.dtsi"
428 #include "imx8-ss-lsio.dtsi"
431 #include "imx8qm-ss-img.dtsi"
432 #include "imx8qm-ss-dma.dtsi"
433 #include "imx8qm-ss-conn.dtsi"
434 #include "imx8qm-ss-lsio.dtsi"