Lines Matching +full:0 +full:x52000000

34 		#size-cells = <0>;
62 A53_0: cpu@0 {
65 reg = <0x0 0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
82 reg = <0x0 0x1>;
85 i-cache-size = <0x8000>;
88 d-cache-size = <0x8000>;
99 reg = <0x0 0x2>;
102 i-cache-size = <0x8000>;
105 d-cache-size = <0x8000>;
116 reg = <0x0 0x3>;
119 i-cache-size = <0x8000>;
122 d-cache-size = <0x8000>;
133 reg = <0x0 0x100>;
136 i-cache-size = <0xC000>;
139 d-cache-size = <0x8000>;
150 reg = <0x0 0x101>;
162 cache-size = <0x100000>;
171 cache-size = <0x100000>;
177 a53_opp_table: opp-table-0 {
239 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
240 <0x0 0x51b00000 0 0xC0000>, /* GICR */
241 <0x0 0x52000000 0 0x2000>, /* GICC */
242 <0x0 0x52010000 0 0x1000>, /* GICH */
243 <0x0 0x52020000 0 0x20000>; /* GICV */
271 reg = <0 0x51400000 0 0x40000>;
314 mboxes = <&lsio_mu1 0 0
315 &lsio_mu1 1 0
343 reg = <0x1c4 6>;
347 reg = <0x1c6 6>;
481 #clock-cells = <0>;
482 clock-frequency = <0>;
488 #clock-cells = <0>;
489 clock-frequency = <0>;
495 #clock-cells = <0>;
496 clock-frequency = <0>;
502 #clock-cells = <0>;
503 clock-frequency = <0>;
509 #clock-cells = <0>;
510 clock-frequency = <0>;
516 #clock-cells = <0>;
517 clock-frequency = <0>;
523 #clock-cells = <0>;
524 clock-frequency = <0>;
530 #clock-cells = <0>;
531 clock-frequency = <0>;
537 #clock-cells = <0>;
538 clock-frequency = <0>;
544 #clock-cells = <0>;
545 clock-frequency = <0>;
551 #clock-cells = <0>;
552 clock-frequency = <0>;
558 #clock-cells = <0>;
559 clock-frequency = <0>;
565 #clock-cells = <0>;
572 #clock-cells = <0>;
579 #clock-cells = <0>;