Lines Matching +full:imx7ulp +full:- +full:clock

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2018-2019 NXP
8 	uart4_lpcg: clock-controller@5a4a0000 {
9 		compatible = "fsl,imx8qxp-lpcg";
11 		#clock-cells = <1>;
14 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
15 		clock-output-names = "uart4_lpcg_baud_clk",
17 		power-domains = <&pd IMX_SC_R_UART_4>;
20 	can1_lpcg: clock-controller@5ace0000 {
21 		compatible = "fsl,imx8qxp-lpcg";
23 		#clock-cells = <1>;
26 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
27 		clock-output-names = "can1_lpcg_pe_clk",
30 		power-domains = <&pd IMX_SC_R_CAN_1>;
33 	can2_lpcg: clock-controller@5acf0000 {
34 		compatible = "fsl,imx8qxp-lpcg";
36 		#clock-cells = <1>;
39 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
40 		clock-output-names = "can2_lpcg_pe_clk",
43 		power-domains = <&pd IMX_SC_R_CAN_2>;
49 	#dma-cells = <3>;
50 	dma-channels = <22>;
51 	dma-channel-mask = <0xf00>;
74 	power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
100 	power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
111 	fsl,clk-source = /bits/ 8 <1>;
117 	assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>;
118 	fsl,clk-source = /bits/ 8 <1>;
124 	assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>;
125 	fsl,clk-source = /bits/ 8 <1>;
129 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
131 	dma-names = "rx","tx";
135 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
137 	dma-names = "rx","tx";
141 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
143 	dma-names = "rx","tx";
147 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
149 	dma-names = "rx","tx";
153 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
157 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
161 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
165 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";