Lines Matching +full:0 +full:x000400000
47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #size-cells = <0>;
105 A53_0: cpu@0 {
108 reg = <0x0>;
112 i-cache-size = <0x8000>;
115 d-cache-size = <0x8000>;
128 reg = <0x1>;
132 i-cache-size = <0x8000>;
135 d-cache-size = <0x8000>;
146 reg = <0x2>;
150 i-cache-size = <0x8000>;
153 d-cache-size = <0x8000>;
164 reg = <0x3>;
168 i-cache-size = <0x8000>;
171 d-cache-size = <0x8000>;
183 cache-size = <0x100000>;
197 opp-supported-hw = <0xf>, <0x4>;
206 opp-supported-hw = <0xe>, <0x3>;
214 opp-supported-hw = <0xc>, <0x4>;
222 opp-supported-hw = <0x8>, <0x3>;
237 #size-cells = <0>;
239 port@0 {
240 reg = <0>;
296 thermal-sensors = <&tmu 0>;
377 soc: soc@0 {
381 ranges = <0x0 0x0 0x0 0x3e000000>;
382 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
388 reg = <0x28440000 0x1000>;
404 reg = <0x28540000 0x1000>;
420 reg = <0x28640000 0x1000>;
436 reg = <0x28740000 0x1000>;
452 reg = <0x28c03000 0x1000>;
458 #size-cells = <0>;
460 port@0 {
461 reg = <0>;
489 reg = <0x28c04000 0x1000>;
512 reg = <0x28c06000 0x1000>;
527 reg = <0x30000000 0x400000>;
530 ranges = <0x30000000 0x30000000 0x400000>;
533 #sound-dai-cells = <0>;
535 reg = <0x30010000 0x10000>;
541 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
547 #sound-dai-cells = <0>;
549 reg = <0x30030000 0x10000>;
555 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
561 #sound-dai-cells = <0>;
563 reg = <0x30040000 0x10000>;
569 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
575 #sound-dai-cells = <0>;
577 reg = <0x30050000 0x10000>;
583 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
590 reg = <0x30200000 0x10000>;
598 gpio-ranges = <&iomuxc 0 10 30>;
603 reg = <0x30210000 0x10000>;
611 gpio-ranges = <&iomuxc 0 40 21>;
616 reg = <0x30220000 0x10000>;
624 gpio-ranges = <&iomuxc 0 61 26>;
629 reg = <0x30230000 0x10000>;
637 gpio-ranges = <&iomuxc 0 87 32>;
642 reg = <0x30240000 0x10000>;
650 gpio-ranges = <&iomuxc 0 119 30>;
655 reg = <0x30260000 0x10000>;
659 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
660 fsl,tmu-calibration = <0x00000000 0x00000023>,
661 <0x00000001 0x00000029>,
662 <0x00000002 0x0000002f>,
663 <0x00000003 0x00000035>,
664 <0x00000004 0x0000003d>,
665 <0x00000005 0x00000043>,
666 <0x00000006 0x0000004b>,
667 <0x00000007 0x00000051>,
668 <0x00000008 0x00000057>,
669 <0x00000009 0x0000005f>,
670 <0x0000000a 0x00000067>,
671 <0x0000000b 0x0000006f>,
673 <0x00010000 0x0000001b>,
674 <0x00010001 0x00000023>,
675 <0x00010002 0x0000002b>,
676 <0x00010003 0x00000033>,
677 <0x00010004 0x0000003b>,
678 <0x00010005 0x00000043>,
679 <0x00010006 0x0000004b>,
680 <0x00010007 0x00000055>,
681 <0x00010008 0x0000005d>,
682 <0x00010009 0x00000067>,
683 <0x0001000a 0x00000070>,
685 <0x00020000 0x00000017>,
686 <0x00020001 0x00000023>,
687 <0x00020002 0x0000002d>,
688 <0x00020003 0x00000037>,
689 <0x00020004 0x00000041>,
690 <0x00020005 0x0000004b>,
691 <0x00020006 0x00000057>,
692 <0x00020007 0x00000063>,
693 <0x00020008 0x0000006f>,
695 <0x00030000 0x00000015>,
696 <0x00030001 0x00000021>,
697 <0x00030002 0x0000002d>,
698 <0x00030003 0x00000039>,
699 <0x00030004 0x00000045>,
700 <0x00030005 0x00000053>,
701 <0x00030006 0x0000005f>,
702 <0x00030007 0x00000071>;
708 reg = <0x30280000 0x10000>;
716 reg = <0x30290000 0x10000>;
724 reg = <0x302a0000 0x10000>;
732 reg = <0x302c0000 0x10000>;
743 reg = <0x30320000 0x10000>;
756 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
768 reg = <0x30330000 0x10000>;
773 reg = <0x30340000 0x10000>;
778 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
784 reg = <0x30350000 0x10000>;
795 * Fuse Address = (ADDR * 4) + 0x400
798 * +0x10 in Fusemap Description Table (e.g.
799 * reg = <0x4 0x8> describes fuses 0x410 and
800 * 0x420).
802 imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */
803 reg = <0x4 0x8>;
806 cpu_speed_grade: speed-grade@10 { /* 0x440 */
807 reg = <0x10 4>;
810 fec_mac_address: mac-address@90 { /* 0x640 */
811 reg = <0x90 6>;
817 reg = <0x30360000 0x10000>;
823 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
824 reg = <0x30370000 0x10000>;
827 compatible = "fsl,sec-v4.0-mon-rtc-lp";
829 offset = <0x34>;
837 compatible = "fsl,sec-v4.0-pwrkey";
850 reg = <0x30380000 0x10000>;
868 assigned-clock-rates = <0>, <0>,
870 <0>,
871 <0>,
872 <0>,
877 <0>,
885 reg = <0x30390000 0x10000>;
892 reg = <0x303a0000 0x10000>;
900 #size-cells = <0>;
902 pgc_mipi: power-domain@0 {
903 #power-domain-cells = <0>;
923 #power-domain-cells = <0>;
929 #power-domain-cells = <0>;
934 #power-domain-cells = <0>;
939 #power-domain-cells = <0>;
944 #power-domain-cells = <0>;
953 #power-domain-cells = <0>;
969 <0>;
973 #power-domain-cells = <0>;
978 #power-domain-cells = <0>;
983 #power-domain-cells = <0>;
988 #power-domain-cells = <0>;
997 reg = <0x30400000 0x400000>;
1000 ranges = <0x30400000 0x30400000 0x400000>;
1004 reg = <0x30660000 0x10000>;
1015 reg = <0x30670000 0x10000>;
1026 reg = <0x30680000 0x10000>;
1037 reg = <0x30690000 0x10000>;
1048 reg = <0x306a0000 0x20000>;
1057 reg = <0x30800000 0x400000>;
1060 ranges = <0x30800000 0x30800000 0x400000>,
1061 <0x08000000 0x08000000 0x10000000>;
1065 reg = <0x30810000 0x10000>;
1082 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
1089 #size-cells = <0>;
1091 reg = <0x30820000 0x10000>;
1096 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1103 #size-cells = <0>;
1105 reg = <0x30830000 0x10000>;
1117 #size-cells = <0>;
1119 reg = <0x30840000 0x10000>;
1132 reg = <0x30860000 0x10000>;
1137 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1145 reg = <0x30880000 0x10000>;
1150 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1158 reg = <0x30890000 0x10000>;
1163 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1170 reg = <0x308a0000 0x10000>;
1187 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
1193 #sound-dai-cells = <0>;
1195 reg = <0x308b0000 0x10000>;
1201 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
1207 #sound-dai-cells = <0>;
1209 reg = <0x308c0000 0x10000>;
1215 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
1221 compatible = "fsl,sec-v4.0";
1224 reg = <0x30900000 0x40000>;
1225 ranges = <0 0x30900000 0x40000>;
1232 compatible = "fsl,sec-v4.0-job-ring";
1233 reg = <0x1000 0x1000>;
1239 compatible = "fsl,sec-v4.0-job-ring";
1240 reg = <0x2000 0x1000>;
1245 compatible = "fsl,sec-v4.0-job-ring";
1246 reg = <0x3000 0x1000>;
1253 reg = <0x30a00000 0x300>;
1255 #size-cells = <0>;
1269 mux-controls = <&mux 0>;
1282 #size-cells = <0>;
1284 port@0 {
1285 reg = <0>;
1287 #size-cells = <0>;
1288 mipi_dsi_lcdif_in: endpoint@0 {
1289 reg = <0>;
1298 reg = <0x30a00300 0x100>;
1308 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
1309 #phy-cells = <0>;
1316 reg = <0x30a20000 0x10000>;
1320 #size-cells = <0>;
1326 reg = <0x30a30000 0x10000>;
1330 #size-cells = <0>;
1336 reg = <0x30a40000 0x10000>;
1340 #size-cells = <0>;
1346 reg = <0x30a50000 0x10000>;
1350 #size-cells = <0>;
1357 reg = <0x30a60000 0x10000>;
1362 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1369 reg = <0x30a70000 0x1000>;
1385 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
1392 #size-cells = <0>;
1406 reg = <0x30a90000 0x10000>;
1421 reg = <0x30b60000 0x1000>;
1437 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
1444 #size-cells = <0>;
1458 reg = <0x30b80000 0x10000>;
1473 reg = <0x30aa0000 0x10000>;
1482 reg = <0x30b40000 0x10000>;
1497 reg = <0x30b50000 0x10000>;
1511 #size-cells = <0>;
1513 reg = <0x30bb0000 0x10000>,
1514 <0x08000000 0x10000000>;
1525 reg = <0x30bd0000 0x10000>;
1536 reg = <0x30be0000 0x10000>;
1556 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1561 fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
1568 reg = <0x32700000 0x100000>;
1593 reg = <0x32c00000 0x400000>;
1596 ranges = <0x32c00000 0x32c00000 0x400000>;
1600 reg = <0x32e2d000 0x1000>;
1604 fsl,channel = <0>;
1613 reg = <0x38000000 0x40000>;
1632 <800000000>, <800000000>, <0>;
1638 reg = <0x38100000 0x10000>;
1658 reg = <0x381f0040 0x40>;
1664 #phy-cells = <0>;
1670 reg = <0x38200000 0x10000>;
1690 reg = <0x382f0040 0x40>;
1696 #phy-cells = <0>;
1702 reg = <0x38300000 0x10000>;
1710 reg = <0x38310000 0x10000>;
1718 reg = <0x38320000 0x100>;
1729 reg = <0x33800000 0x400000>,
1730 <0x1ff00000 0x80000>;
1735 bus-range = <0x00 0xff>;
1736 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1737 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1742 interrupt-map-mask = <0 0 0 0x7>;
1743 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1744 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1745 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1746 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1748 linux,pci-domain = <0>;
1772 reg = <0x33c00000 0x400000>,
1773 <0x27f00000 0x80000>;
1778 bus-range = <0x00 0xff>;
1779 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */
1780 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1785 interrupt-map-mask = <0 0 0 0x7>;
1786 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1787 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1788 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1789 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1815 reg = <0x33c00000 0x000400000>,
1816 <0x20000000 0x08000000>;
1847 reg = <0x38800000 0x10000>, /* GIC Dist */
1848 <0x38880000 0xc0000>, /* GICR */
1849 <0x31000000 0x2000>, /* GICC */
1850 <0x31010000 0x2000>, /* GICV */
1851 <0x31020000 0x2000>; /* GICH */
1860 reg = <0x3d400000 0x400000>;
1871 reg = <0x3d800000 0x400000>;