Lines Matching +full:0 +full:xcd

20 	pinctrl-0 = <&pinctrl_fec1>;
28 #size-cells = <0>;
41 pinctrl-0 = <&pinctrl_i2c1>;
47 reg = <0x08>;
131 reg = <0x50>;
146 pinctrl-0 = <&pinctrl_qspi>;
150 spi_flash: flash@0 {
153 reg = <0>;
162 pinctrl-0 = <&pinctrl_uart1>;
171 pinctrl-0 = <&pinctrl_uart4>;
182 pinctrl-0 = <&pinctrl_usdhc1>;
192 pinctrl-0 = <&pinctrl_wdog>;
200 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
201 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
202 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
203 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
204 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
205 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
206 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
207 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
208 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
209 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
210 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
211 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
212 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
213 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
214 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
220 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
221 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
227 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x74
228 MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x16
229 MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
235 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
236 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
237 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
238 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
239 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
240 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
247 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
248 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
249 MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
255 MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49
256 MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49
257 MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19
263 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
264 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
265 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
266 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
267 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
268 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
269 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
270 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
271 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
272 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
273 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
274 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
280 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
281 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
282 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
283 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
284 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
285 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
286 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
287 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
288 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
289 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
290 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
291 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
297 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
298 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
299 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
300 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
301 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
302 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
303 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
304 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
305 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
306 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
307 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
308 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
314 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6