Lines Matching +full:pcie +full:- +full:ob
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
47 #address-cells = <1>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a53";
54 clock-latency = <61036>;
56 enable-method = "psci";
57 i-cache-size = <0x8000>;
58 i-cache-line-size = <64>;
59 i-cache-sets = <256>;
60 d-cache-size = <0x8000>;
61 d-cache-line-size = <64>;
62 d-cache-sets = <128>;
63 next-level-cache = <&A53_L2>;
64 nvmem-cells = <&cpu_speed_grade>;
65 nvmem-cell-names = "speed_grade";
66 operating-points-v2 = <&a53_opp_table>;
67 #cooling-cells = <2>;
72 compatible = "arm,cortex-a53";
74 clock-latency = <61036>;
76 enable-method = "psci";
77 i-cache-size = <0x8000>;
78 i-cache-line-size = <64>;
79 i-cache-sets = <256>;
80 d-cache-size = <0x8000>;
81 d-cache-line-size = <64>;
82 d-cache-sets = <128>;
83 next-level-cache = <&A53_L2>;
84 operating-points-v2 = <&a53_opp_table>;
85 #cooling-cells = <2>;
90 compatible = "arm,cortex-a53";
92 clock-latency = <61036>;
94 enable-method = "psci";
95 i-cache-size = <0x8000>;
96 i-cache-line-size = <64>;
97 i-cache-sets = <256>;
98 d-cache-size = <0x8000>;
99 d-cache-line-size = <64>;
100 d-cache-sets = <128>;
101 next-level-cache = <&A53_L2>;
102 operating-points-v2 = <&a53_opp_table>;
103 #cooling-cells = <2>;
108 compatible = "arm,cortex-a53";
110 clock-latency = <61036>;
112 enable-method = "psci";
113 i-cache-size = <0x8000>;
114 i-cache-line-size = <64>;
115 i-cache-sets = <256>;
116 d-cache-size = <0x8000>;
117 d-cache-line-size = <64>;
118 d-cache-sets = <128>;
119 next-level-cache = <&A53_L2>;
120 operating-points-v2 = <&a53_opp_table>;
121 #cooling-cells = <2>;
124 A53_L2: l2-cache0 {
126 cache-unified;
127 cache-level = <2>;
128 cache-size = <0x80000>;
129 cache-line-size = <64>;
130 cache-sets = <512>;
134 a53_opp_table: opp-table {
135 compatible = "operating-points-v2";
136 opp-shared;
138 opp-1200000000 {
139 opp-hz = /bits/ 64 <1200000000>;
140 opp-microvolt = <850000>;
141 opp-supported-hw = <0x8a0>, <0x7>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
146 opp-1600000000 {
147 opp-hz = /bits/ 64 <1600000000>;
148 opp-microvolt = <950000>;
149 opp-supported-hw = <0xa0>, <0x7>;
150 clock-latency-ns = <150000>;
151 opp-suspend;
154 opp-1800000000 {
155 opp-hz = /bits/ 64 <1800000000>;
156 opp-microvolt = <1000000>;
157 opp-supported-hw = <0x20>, <0x3>;
158 clock-latency-ns = <150000>;
159 opp-suspend;
163 osc_32k: clock-osc-32k {
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <32768>;
167 clock-output-names = "osc_32k";
170 osc_24m: clock-osc-24m {
171 compatible = "fixed-clock";
172 #clock-cells = <0>;
173 clock-frequency = <24000000>;
174 clock-output-names = "osc_24m";
177 clk_ext1: clock-ext1 {
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <133000000>;
181 clock-output-names = "clk_ext1";
184 clk_ext2: clock-ext2 {
185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency = <133000000>;
188 clock-output-names = "clk_ext2";
191 clk_ext3: clock-ext3 {
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext3";
198 clk_ext4: clock-ext4 {
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <133000000>;
202 clock-output-names = "clk_ext4";
207 * non-configurable funnel don't show up on the AMBA
210 compatible = "arm,coresight-static-funnel";
212 in-ports {
213 #address-cells = <1>;
214 #size-cells = <0>;
220 remote-endpoint = <&etm0_out_port>;
228 remote-endpoint = <&etm1_out_port>;
236 remote-endpoint = <&etm2_out_port>;
244 remote-endpoint = <&etm3_out_port>;
249 out-ports {
253 remote-endpoint = <&hugo_funnel_in_port0>;
259 reserved-memory {
260 #address-cells = <2>;
261 #size-cells = <2>;
266 no-map;
272 compatible = "arm,cortex-a53-pmu";
278 compatible = "arm,psci-1.0";
282 thermal-zones {
283 cpu-thermal {
284 polling-delay-passive = <250>;
285 polling-delay = <2000>;
286 thermal-sensors = <&tmu 0>;
301 cooling-maps {
304 cooling-device =
313 soc-thermal {
314 polling-delay-passive = <250>;
315 polling-delay = <2000>;
316 thermal-sensors = <&tmu 1>;
331 cooling-maps {
334 cooling-device =
345 compatible = "arm,armv8-timer";
350 clock-frequency = <8000000>;
351 arm,no-tick-in-suspend;
355 compatible = "fsl,imx8mp-soc", "simple-bus";
356 #address-cells = <1>;
357 #size-cells = <1>;
359 nvmem-cells = <&imx8mp_uid>;
360 nvmem-cell-names = "soc_unique_id";
363 compatible = "arm,coresight-etm4x", "arm,primecell";
367 clock-names = "apb_pclk";
369 out-ports {
372 remote-endpoint = <&ca_funnel_in_port0>;
379 compatible = "arm,coresight-etm4x", "arm,primecell";
383 clock-names = "apb_pclk";
385 out-ports {
388 remote-endpoint = <&ca_funnel_in_port1>;
395 compatible = "arm,coresight-etm4x", "arm,primecell";
399 clock-names = "apb_pclk";
401 out-ports {
404 remote-endpoint = <&ca_funnel_in_port2>;
411 compatible = "arm,coresight-etm4x", "arm,primecell";
415 clock-names = "apb_pclk";
417 out-ports {
420 remote-endpoint = <&ca_funnel_in_port3>;
427 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
430 clock-names = "apb_pclk";
432 in-ports {
433 #address-cells = <1>;
434 #size-cells = <0>;
440 remote-endpoint = <&ca_funnel_out_port0>;
462 out-ports {
465 remote-endpoint = <&etf_in_port>;
472 compatible = "arm,coresight-tmc", "arm,primecell";
475 clock-names = "apb_pclk";
477 in-ports {
480 remote-endpoint = <&hugo_funnel_out_port0>;
485 out-ports {
488 remote-endpoint = <&etr_in_port>;
495 compatible = "arm,coresight-tmc", "arm,primecell";
498 clock-names = "apb_pclk";
500 in-ports {
503 remote-endpoint = <&etf_out_port>;
510 compatible = "fsl,aips-bus", "simple-bus";
512 #address-cells = <1>;
513 #size-cells = <1>;
517 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
522 gpio-controller;
523 #gpio-cells = <2>;
524 interrupt-controller;
525 #interrupt-cells = <2>;
526 gpio-ranges = <&iomuxc 0 5 30>;
530 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
535 gpio-controller;
536 #gpio-cells = <2>;
537 interrupt-controller;
538 #interrupt-cells = <2>;
539 gpio-ranges = <&iomuxc 0 35 21>;
543 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
548 gpio-controller;
549 #gpio-cells = <2>;
550 interrupt-controller;
551 #interrupt-cells = <2>;
552 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
556 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
561 gpio-controller;
562 #gpio-cells = <2>;
563 interrupt-controller;
564 #interrupt-cells = <2>;
565 gpio-ranges = <&iomuxc 0 82 32>;
569 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
574 gpio-controller;
575 #gpio-cells = <2>;
576 interrupt-controller;
577 #interrupt-cells = <2>;
578 gpio-ranges = <&iomuxc 0 114 30>;
582 compatible = "fsl,imx8mp-tmu";
585 nvmem-cells = <&tmu_calib>;
586 nvmem-cell-names = "calib";
587 #thermal-sensor-cells = <1>;
591 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
599 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
607 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
615 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
619 clock-names = "ipg", "per";
623 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
627 clock-names = "ipg", "per";
631 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
635 clock-names = "ipg", "per";
639 compatible = "fsl,imx8mp-iomuxc";
644 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
649 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
653 #address-cells = <1>;
654 #size-cells = <1>;
669 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
673 cpu_speed_grade: speed-grade@10 { /* 0x440 */
677 eth_mac1: mac-address@90 { /* 0x640 */
681 eth_mac2: mac-address@96 { /* 0x658 */
685 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
690 anatop: clock-controller@30360000 {
691 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
693 #clock-cells = <1>;
697 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
700 snvs_rtc: snvs-rtc-lp {
701 compatible = "fsl,sec-v4.0-mon-rtc-lp";
707 clock-names = "snvs-rtc";
710 snvs_pwrkey: snvs-powerkey {
711 compatible = "fsl,sec-v4.0-pwrkey";
715 clock-names = "snvs-pwrkey";
717 wakeup-source;
721 snvs_lpgpr: snvs-lpgpr {
722 compatible = "fsl,imx8mp-snvs-lpgpr",
723 "fsl,imx7d-snvs-lpgpr";
727 clk: clock-controller@30380000 {
728 compatible = "fsl,imx8mp-ccm";
732 #clock-cells = <1>;
735 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
737 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
742 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
747 assigned-clock-rates = <0>, <0>,
753 src: reset-controller@30390000 {
754 compatible = "fsl,imx8mp-src", "syscon";
757 #reset-cells = <1>;
761 compatible = "fsl,imx8mp-gpc";
763 interrupt-parent = <&gic>;
765 interrupt-controller;
766 #interrupt-cells = <3>;
769 #address-cells = <1>;
770 #size-cells = <0>;
772 pgc_mipi_phy1: power-domain@0 {
773 #power-domain-cells = <0>;
777 pgc_pcie_phy: power-domain@1 {
778 #power-domain-cells = <0>;
782 pgc_usb1_phy: power-domain@2 {
783 #power-domain-cells = <0>;
787 pgc_usb2_phy: power-domain@3 {
788 #power-domain-cells = <0>;
792 pgc_audio: power-domain@5 {
793 #power-domain-cells = <0>;
797 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
799 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
801 assigned-clock-rates = <400000000>,
805 pgc_gpu2d: power-domain@6 {
806 #power-domain-cells = <0>;
809 power-domains = <&pgc_gpumix>;
812 pgc_gpumix: power-domain@7 {
813 #power-domain-cells = <0>;
817 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
819 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
821 assigned-clock-rates = <800000000>, <400000000>;
824 pgc_gpu3d: power-domain@9 {
825 #power-domain-cells = <0>;
829 power-domains = <&pgc_gpumix>;
832 pgc_mediamix: power-domain@10 {
833 #power-domain-cells = <0>;
839 pgc_mipi_phy2: power-domain@16 {
840 #power-domain-cells = <0>;
844 pgc_hsiomix: power-domain@17 {
845 #power-domain-cells = <0>;
849 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
850 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
851 assigned-clock-rates = <500000000>;
854 pgc_ispdwp: power-domain@18 {
855 #power-domain-cells = <0>;
860 pgc_vpumix: power-domain@19 {
861 #power-domain-cells = <0>;
866 pgc_vpu_g1: power-domain@20 {
867 #power-domain-cells = <0>;
868 power-domains = <&pgc_vpumix>;
873 pgc_vpu_g2: power-domain@21 {
874 #power-domain-cells = <0>;
875 power-domains = <&pgc_vpumix>;
880 pgc_vpu_vc8000e: power-domain@22 {
881 #power-domain-cells = <0>;
882 power-domains = <&pgc_vpumix>;
887 pgc_mlmix: power-domain@24 {
888 #power-domain-cells = <0>;
893 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
896 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
899 assigned-clock-rates = <800000000>,
908 compatible = "fsl,aips-bus", "simple-bus";
910 #address-cells = <1>;
911 #size-cells = <1>;
915 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
920 clock-names = "ipg", "per";
921 #pwm-cells = <3>;
926 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
931 clock-names = "ipg", "per";
932 #pwm-cells = <3>;
937 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
942 clock-names = "ipg", "per";
943 #pwm-cells = <3>;
948 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
953 clock-names = "ipg", "per";
954 #pwm-cells = <3>;
959 compatible = "nxp,sysctr-timer";
963 clock-names = "per";
967 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
971 clock-names = "ipg", "per";
975 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
979 clock-names = "ipg", "per";
983 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
987 clock-names = "ipg", "per";
992 compatible = "fsl,aips-bus", "simple-bus";
994 #address-cells = <1>;
995 #size-cells = <1>;
998 spba-bus@30800000 {
999 compatible = "fsl,spba-bus", "simple-bus";
1001 #address-cells = <1>;
1002 #size-cells = <1>;
1006 #address-cells = <1>;
1007 #size-cells = <0>;
1008 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1013 clock-names = "ipg", "per";
1014 assigned-clock-rates = <80000000>;
1015 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
1016 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1018 dma-names = "rx", "tx";
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1025 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1030 clock-names = "ipg", "per";
1031 assigned-clock-rates = <80000000>;
1032 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
1033 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1035 dma-names = "rx", "tx";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1042 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1047 clock-names = "ipg", "per";
1048 assigned-clock-rates = <80000000>;
1049 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
1050 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1052 dma-names = "rx", "tx";
1057 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1062 clock-names = "ipg", "per";
1064 dma-names = "rx", "tx";
1069 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1074 clock-names = "ipg", "per";
1076 dma-names = "rx", "tx";
1081 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1086 clock-names = "ipg", "per";
1088 dma-names = "rx", "tx";
1093 compatible = "fsl,imx8mp-flexcan";
1098 clock-names = "ipg", "per";
1099 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
1100 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1101 assigned-clock-rates = <40000000>;
1102 fsl,clk-source = /bits/ 8 <0>;
1103 fsl,stop-mode = <&gpr 0x10 4>;
1108 compatible = "fsl,imx8mp-flexcan";
1113 clock-names = "ipg", "per";
1114 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
1115 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1116 assigned-clock-rates = <40000000>;
1117 fsl,clk-source = /bits/ 8 <0>;
1118 fsl,stop-mode = <&gpr 0x10 5>;
1124 compatible = "fsl,sec-v4.0";
1125 #address-cells = <1>;
1126 #size-cells = <1>;
1132 clock-names = "aclk", "ipg";
1135 compatible = "fsl,sec-v4.0-job-ring";
1142 compatible = "fsl,sec-v4.0-job-ring";
1148 compatible = "fsl,sec-v4.0-job-ring";
1155 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1156 #address-cells = <1>;
1157 #size-cells = <0>;
1165 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1175 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1176 #address-cells = <1>;
1177 #size-cells = <0>;
1185 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1195 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1200 clock-names = "ipg", "per";
1202 dma-names = "rx", "tx";
1207 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1211 #mbox-cells = <2>;
1215 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1218 #mbox-cells = <2>;
1223 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1233 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1234 #address-cells = <1>;
1235 #size-cells = <0>;
1243 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1249 clock-names = "ipg", "ahb", "per";
1250 fsl,tuning-start-tap = <20>;
1251 fsl,tuning-step = <2>;
1252 bus-width = <4>;
1257 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1263 clock-names = "ipg", "ahb", "per";
1264 fsl,tuning-start-tap = <20>;
1265 fsl,tuning-step = <2>;
1266 bus-width = <4>;
1271 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1277 clock-names = "ipg", "ahb", "per";
1278 fsl,tuning-start-tap = <20>;
1279 fsl,tuning-step = <2>;
1280 bus-width = <4>;
1285 compatible = "nxp,imx8mp-fspi";
1287 reg-names = "fspi_base", "fspi_mmap";
1291 clock-names = "fspi_en", "fspi";
1292 assigned-clock-rates = <80000000>;
1293 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
1294 #address-cells = <1>;
1295 #size-cells = <0>;
1299 sdma1: dma-controller@30bd0000 {
1300 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1305 clock-names = "ipg", "ahb";
1306 #dma-cells = <3>;
1307 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1311 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1322 clock-names = "ipg", "ahb", "ptp",
1324 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1328 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1332 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1333 fsl,num-tx-queues = <3>;
1334 fsl,num-rx-queues = <3>;
1335 nvmem-cells = <ð_mac1>;
1336 nvmem-cell-names = "mac-address";
1337 fsl,stop-mode = <&gpr 0x10 3>;
1342 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1346 interrupt-names = "macirq", "eth_wake_irq";
1351 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1352 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1355 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1358 assigned-clock-rates = <0>, <100000000>, <125000000>;
1359 nvmem-cells = <ð_mac2>;
1360 nvmem-cell-names = "mac-address";
1367 compatible = "fsl,aips-bus", "simple-bus";
1369 #address-cells = <1>;
1370 #size-cells = <1>;
1373 spba-bus@30c00000 {
1374 compatible = "fsl,spba-bus", "simple-bus";
1376 #address-cells = <1>;
1377 #size-cells = <1>;
1381 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1383 #sound-dai-cells = <0>;
1389 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1391 dma-names = "rx", "tx";
1397 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1399 #sound-dai-cells = <0>;
1405 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1407 dma-names = "rx", "tx";
1413 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1415 #sound-dai-cells = <0>;
1421 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1423 dma-names = "rx", "tx";
1429 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1431 #sound-dai-cells = <0>;
1437 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1439 dma-names = "rx", "tx";
1445 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1447 #sound-dai-cells = <0>;
1453 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1455 dma-names = "rx", "tx";
1461 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1463 #sound-dai-cells = <0>;
1469 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1471 dma-names = "rx", "tx";
1477 compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc";
1481 clock-names = "mem";
1486 dma-names = "ctx0_rx", "ctx0_tx",
1490 firmware-name = "imx/easrc/easrc-imx8mn.bin";
1491 fsl,asrc-rate = <8000>;
1492 fsl,asrc-format = <2>;
1496 micfil: audio-controller@30ca0000 {
1497 compatible = "fsl,imx8mp-micfil";
1499 #sound-dai-cells = <0>;
1509 clock-names = "ipg_clk", "ipg_clk_app",
1512 dma-names = "rx";
1518 sdma3: dma-controller@30e00000 {
1519 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1521 #dma-cells = <3>;
1524 clock-names = "ipg", "ahb";
1526 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1529 sdma2: dma-controller@30e10000 {
1530 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1532 #dma-cells = <3>;
1535 clock-names = "ipg", "ahb";
1537 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1540 audio_blk_ctrl: clock-controller@30e20000 {
1541 compatible = "fsl,imx8mp-audio-blk-ctrl";
1543 #clock-cells = <1>;
1551 clock-names = "ahb",
1554 power-domains = <&pgc_audio>;
1559 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1562 #interconnect-cells = <1>;
1563 operating-points-v2 = <&noc_opp_table>;
1565 noc_opp_table: opp-table {
1566 compatible = "operating-points-v2";
1568 opp-200000000 {
1569 opp-hz = /bits/ 64 <200000000>;
1572 opp-1000000000 {
1573 opp-hz = /bits/ 64 <1000000000>;
1579 compatible = "fsl,aips-bus", "simple-bus";
1581 #address-cells = <1>;
1582 #size-cells = <1>;
1586 compatible = "fsl,imx8mp-isi";
1592 clock-names = "axi", "apb";
1593 fsl,blk-ctrl = <&media_blk_ctrl>;
1594 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
1598 #address-cells = <1>;
1599 #size-cells = <0>;
1605 remote-endpoint = <&mipi_csi_0_out>;
1613 remote-endpoint = <&mipi_csi_1_out>;
1620 compatible = "nxp,imx8mp-dw100";
1625 clock-names = "axi", "ahb";
1626 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
1630 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1633 clock-frequency = <500000000>;
1638 clock-names = "pclk", "wrap", "phy", "axi";
1639 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
1640 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1641 assigned-clock-rates = <500000000>;
1642 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1657 remote-endpoint = <&isi_in_0>;
1664 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1667 clock-frequency = <266000000>;
1672 clock-names = "pclk", "wrap", "phy", "axi";
1673 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
1674 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1675 assigned-clock-rates = <266000000>;
1676 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
1680 #address-cells = <1>;
1681 #size-cells = <0>;
1691 remote-endpoint = <&isi_in_1>;
1698 compatible = "fsl,imx8mp-mipi-dsim";
1702 clock-names = "bus_clk", "sclk_mipi";
1703 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
1705 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1707 assigned-clock-rates = <200000000>, <24000000>;
1708 samsung,pll-clock-frequency = <24000000>;
1710 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
1714 #address-cells = <1>;
1715 #size-cells = <0>;
1721 remote-endpoint = <&lcdif1_to_dsim>;
1727 lcdif1: display-controller@32e80000 {
1728 compatible = "fsl,imx8mp-lcdif";
1733 clock-names = "pix", "axi", "disp_axi";
1735 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
1740 remote-endpoint = <&dsim_from_lcdif1>;
1745 lcdif2: display-controller@32e90000 {
1746 compatible = "fsl,imx8mp-lcdif";
1752 clock-names = "pix", "axi", "disp_axi";
1753 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
1758 remote-endpoint = <&ldb_from_lcdif2>;
1763 media_blk_ctrl: blk-ctrl@32ec0000 {
1764 compatible = "fsl,imx8mp-media-blk-ctrl",
1767 #address-cells = <1>;
1768 #size-cells = <1>;
1769 power-domains = <&pgc_mediamix>,
1779 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1780 "lcdif1", "isi", "mipi-csi2",
1782 "mipi-dsi2";
1792 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1803 clock-names = "apb", "axi", "cam1", "cam2",
1806 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1811 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1815 assigned-clock-rates = <500000000>, <200000000>,
1817 #power-domain-cells = <1>;
1820 compatible = "fsl,imx8mp-ldb";
1822 reg-names = "ldb", "lvds";
1824 clock-names = "ldb";
1825 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1826 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
1830 #address-cells = <1>;
1831 #size-cells = <0>;
1837 remote-endpoint = <&lcdif2_to_ldb>;
1858 pcie_phy: pcie-phy@32f00000 {
1859 compatible = "fsl,imx8mp-pcie-phy";
1863 reset-names = "pciephy", "perst";
1864 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
1865 #phy-cells = <0>;
1869 hsio_blk_ctrl: blk-ctrl@32f10000 {
1870 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1874 clock-names = "usb", "pcie";
1875 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1878 power-domain-names = "bus", "usb", "usb-phy1",
1879 "usb-phy2", "pcie", "pcie-phy";
1884 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
1885 #power-domain-cells = <1>;
1886 #clock-cells = <0>;
1890 pcie: pcie@33800000 {
1891 compatible = "fsl,imx8mp-pcie";
1893 reg-names = "dbi", "config";
1897 clock-names = "pcie", "pcie_bus", "pcie_aux";
1898 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
1899 assigned-clock-rates = <10000000>;
1900 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
1901 #address-cells = <3>;
1902 #size-cells = <2>;
1904 bus-range = <0x00 0xff>;
1906 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1907 num-lanes = <1>;
1908 num-viewport = <4>;
1910 interrupt-names = "msi";
1911 #interrupt-cells = <1>;
1912 interrupt-map-mask = <0 0 0 0x7>;
1913 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1917 fsl,max-link-speed = <3>;
1918 linux,pci-domain = <0>;
1919 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1922 reset-names = "apps", "turnoff";
1924 phy-names = "pcie-phy";
1928 pcie_ep: pcie-ep@33800000 {
1929 compatible = "fsl,imx8mp-pcie-ep";
1931 reg-names = "dbi", "addr_space";
1935 clock-names = "pcie", "pcie_bus", "pcie_aux";
1936 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
1937 assigned-clock-rates = <10000000>;
1938 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
1939 num-lanes = <1>;
1941 interrupt-names = "dma";
1942 fsl,max-link-speed = <3>;
1943 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1946 reset-names = "apps", "turnoff";
1948 phy-names = "pcie-phy";
1949 num-ib-windows = <4>;
1950 num-ob-windows = <4>;
1962 clock-names = "core", "shader", "bus", "reg";
1963 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
1965 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1967 assigned-clock-rates = <800000000>, <800000000>;
1968 power-domains = <&pgc_gpu3d>;
1978 clock-names = "core", "bus", "reg";
1979 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
1980 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1981 assigned-clock-rates = <800000000>;
1982 power-domains = <&pgc_gpu2d>;
1985 vpu_g1: video-codec@38300000 {
1986 compatible = "nxp,imx8mm-vpu-g1";
1990 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
1991 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
1992 assigned-clock-rates = <600000000>;
1993 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
1996 vpu_g2: video-codec@38310000 {
1997 compatible = "nxp,imx8mq-vpu-g2";
2001 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
2002 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
2003 assigned-clock-rates = <500000000>;
2004 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
2007 vpumix_blk_ctrl: blk-ctrl@38330000 {
2008 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
2010 #power-domain-cells = <1>;
2011 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
2013 power-domain-names = "bus", "g1", "g2", "vc8000e";
2017 clock-names = "g1", "g2", "vc8000e";
2018 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;
2019 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
2020 assigned-clock-rates = <600000000>, <600000000>;
2024 interconnect-names = "g1", "g2", "vc8000e";
2035 clock-names = "core", "shader", "bus", "reg";
2036 power-domains = <&pgc_mlmix>;
2039 gic: interrupt-controller@38800000 {
2040 compatible = "arm,gic-v3";
2043 #interrupt-cells = <3>;
2044 interrupt-controller;
2046 interrupt-parent = <&gic>;
2049 edacmc: memory-controller@3d400000 {
2050 compatible = "snps,ddrc-3.80a";
2055 ddr-pmu@3d800000 {
2056 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
2061 usb3_phy0: usb-phy@381f0040 {
2062 compatible = "fsl,imx8mp-usb-phy";
2065 clock-names = "phy";
2066 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2067 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2068 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
2069 #phy-cells = <0>;
2074 compatible = "fsl,imx8mp-dwc3";
2079 clock-names = "hsio", "suspend";
2081 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2082 #address-cells = <1>;
2083 #size-cells = <1>;
2084 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2094 clock-names = "bus_early", "ref", "suspend";
2097 phy-names = "usb2-phy", "usb3-phy";
2098 snps,gfladj-refclk-lpm-sel-quirk;
2099 snps,parkmode-disable-ss-quirk;
2104 usb3_phy1: usb-phy@382f0040 {
2105 compatible = "fsl,imx8mp-usb-phy";
2108 clock-names = "phy";
2109 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2110 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2111 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
2112 #phy-cells = <0>;
2117 compatible = "fsl,imx8mp-dwc3";
2122 clock-names = "hsio", "suspend";
2124 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2125 #address-cells = <1>;
2126 #size-cells = <1>;
2127 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2137 clock-names = "bus_early", "ref", "suspend";
2140 phy-names = "usb2-phy", "usb3-phy";
2141 snps,gfladj-refclk-lpm-sel-quirk;
2142 snps,parkmode-disable-ss-quirk;
2147 compatible = "fsl,imx8mp-dsp";
2149 mbox-names = "txdb0", "txdb1",
2153 memory-region = <&dsp_reserved>;