Lines Matching +full:0 +full:x000400000
48 #size-cells = <0>;
50 A53_0: cpu@0 {
53 reg = <0x0>;
57 i-cache-size = <0x8000>;
60 d-cache-size = <0x8000>;
73 reg = <0x1>;
77 i-cache-size = <0x8000>;
80 d-cache-size = <0x8000>;
91 reg = <0x2>;
95 i-cache-size = <0x8000>;
98 d-cache-size = <0x8000>;
109 reg = <0x3>;
113 i-cache-size = <0x8000>;
116 d-cache-size = <0x8000>;
128 cache-size = <0x80000>;
141 opp-supported-hw = <0x8a0>, <0x7>;
149 opp-supported-hw = <0xa0>, <0x7>;
157 opp-supported-hw = <0x20>, <0x3>;
165 #clock-cells = <0>;
172 #clock-cells = <0>;
179 #clock-cells = <0>;
186 #clock-cells = <0>;
193 #clock-cells = <0>;
200 #clock-cells = <0>;
214 #size-cells = <0>;
216 port@0 {
217 reg = <0>;
265 reg = <0 0x92400000 0 0x2000000>;
286 thermal-sensors = <&tmu 0>;
354 soc: soc@0 {
358 ranges = <0x0 0x0 0x0 0x3e000000>;
364 reg = <0x28440000 0x1000>;
380 reg = <0x28540000 0x1000>;
396 reg = <0x28640000 0x1000>;
412 reg = <0x28740000 0x1000>;
428 reg = <0x28c03000 0x1000>;
434 #size-cells = <0>;
436 port@0 {
437 reg = <0>;
473 reg = <0x28c04000 0x1000>;
496 reg = <0x28c06000 0x1000>;
511 reg = <0x30000000 0x400000>;
518 reg = <0x30200000 0x10000>;
526 gpio-ranges = <&iomuxc 0 5 30>;
531 reg = <0x30210000 0x10000>;
539 gpio-ranges = <&iomuxc 0 35 21>;
544 reg = <0x30220000 0x10000>;
552 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
557 reg = <0x30230000 0x10000>;
565 gpio-ranges = <&iomuxc 0 82 32>;
570 reg = <0x30240000 0x10000>;
578 gpio-ranges = <&iomuxc 0 114 30>;
583 reg = <0x30260000 0x10000>;
592 reg = <0x30280000 0x10000>;
600 reg = <0x30290000 0x10000>;
608 reg = <0x302a0000 0x10000>;
616 reg = <0x302d0000 0x10000>;
624 reg = <0x302e0000 0x10000>;
632 reg = <0x302f0000 0x10000>;
640 reg = <0x30330000 0x10000>;
645 reg = <0x30340000 0x10000>;
650 reg = <0x30350000 0x10000>;
662 * Fuse Address = (ADDR * 4) + 0x400
665 * +0x10 in Fusemap Description Table (e.g.
666 * reg = <0x8 0x8> describes fuses 0x420 and
667 * 0x430).
669 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
670 reg = <0x8 0x8>;
673 cpu_speed_grade: speed-grade@10 { /* 0x440 */
674 reg = <0x10 4>;
677 eth_mac1: mac-address@90 { /* 0x640 */
678 reg = <0x90 6>;
681 eth_mac2: mac-address@96 { /* 0x658 */
682 reg = <0x96 6>;
685 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
686 reg = <0x264 0x10>;
692 reg = <0x30360000 0x10000>;
697 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
698 reg = <0x30370000 0x10000>;
701 compatible = "fsl,sec-v4.0-mon-rtc-lp";
703 offset = <0x34>;
711 compatible = "fsl,sec-v4.0-pwrkey";
729 reg = <0x30380000 0x10000>;
747 assigned-clock-rates = <0>, <0>,
755 reg = <0x30390000 0x10000>;
762 reg = <0x303a0000 0x1000>;
770 #size-cells = <0>;
772 pgc_mipi_phy1: power-domain@0 {
773 #power-domain-cells = <0>;
778 #power-domain-cells = <0>;
783 #power-domain-cells = <0>;
788 #power-domain-cells = <0>;
793 #power-domain-cells = <0>;
806 #power-domain-cells = <0>;
813 #power-domain-cells = <0>;
825 #power-domain-cells = <0>;
833 #power-domain-cells = <0>;
840 #power-domain-cells = <0>;
845 #power-domain-cells = <0>;
855 #power-domain-cells = <0>;
861 #power-domain-cells = <0>;
867 #power-domain-cells = <0>;
874 #power-domain-cells = <0>;
881 #power-domain-cells = <0>;
888 #power-domain-cells = <0>;
909 reg = <0x30400000 0x400000>;
916 reg = <0x30660000 0x10000>;
927 reg = <0x30670000 0x10000>;
938 reg = <0x30680000 0x10000>;
949 reg = <0x30690000 0x10000>;
960 reg = <0x306a0000 0x20000>;
968 reg = <0x306e0000 0x10000>;
976 reg = <0x306f0000 0x10000>;
984 reg = <0x30700000 0x10000>;
993 reg = <0x30800000 0x400000>;
1000 reg = <0x30800000 0x100000>;
1007 #size-cells = <0>;
1009 reg = <0x30820000 0x10000>;
1017 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1024 #size-cells = <0>;
1026 reg = <0x30830000 0x10000>;
1041 #size-cells = <0>;
1043 reg = <0x30840000 0x10000>;
1058 reg = <0x30860000 0x10000>;
1063 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1070 reg = <0x30880000 0x10000>;
1075 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1082 reg = <0x30890000 0x10000>;
1087 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1094 reg = <0x308c0000 0x10000>;
1102 fsl,clk-source = /bits/ 8 <0>;
1103 fsl,stop-mode = <&gpr 0x10 4>;
1109 reg = <0x308d0000 0x10000>;
1117 fsl,clk-source = /bits/ 8 <0>;
1118 fsl,stop-mode = <&gpr 0x10 5>;
1124 compatible = "fsl,sec-v4.0";
1127 reg = <0x30900000 0x40000>;
1128 ranges = <0 0x30900000 0x40000>;
1135 compatible = "fsl,sec-v4.0-job-ring";
1136 reg = <0x1000 0x1000>;
1142 compatible = "fsl,sec-v4.0-job-ring";
1143 reg = <0x2000 0x1000>;
1148 compatible = "fsl,sec-v4.0-job-ring";
1149 reg = <0x3000 0x1000>;
1157 #size-cells = <0>;
1158 reg = <0x30a20000 0x10000>;
1167 #size-cells = <0>;
1168 reg = <0x30a30000 0x10000>;
1177 #size-cells = <0>;
1178 reg = <0x30a40000 0x10000>;
1187 #size-cells = <0>;
1188 reg = <0x30a50000 0x10000>;
1196 reg = <0x30a60000 0x10000>;
1201 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1208 reg = <0x30aa0000 0x10000>;
1216 reg = <0x30e60000 0x10000>;
1225 #size-cells = <0>;
1226 reg = <0x30ad0000 0x10000>;
1235 #size-cells = <0>;
1236 reg = <0x30ae0000 0x10000>;
1244 reg = <0x30b40000 0x10000>;
1258 reg = <0x30b50000 0x10000>;
1272 reg = <0x30b60000 0x10000>;
1286 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1295 #size-cells = <0>;
1301 reg = <0x30bd0000 0x10000>;
1312 reg = <0x30be0000 0x10000>;
1332 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1337 fsl,stop-mode = <&gpr 0x10 3>;
1343 reg = <0x30bf0000 0x10000>;
1358 assigned-clock-rates = <0>, <100000000>, <125000000>;
1361 intf_mode = <&gpr 0x4>;
1368 reg = <0x30c00000 0x400000>;
1375 reg = <0x30c00000 0x100000>;
1382 reg = <0x30c10000 0x10000>;
1383 #sound-dai-cells = <0>;
1390 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
1398 reg = <0x30c20000 0x10000>;
1399 #sound-dai-cells = <0>;
1406 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
1414 reg = <0x30c30000 0x10000>;
1415 #sound-dai-cells = <0>;
1422 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
1430 reg = <0x30c50000 0x10000>;
1431 #sound-dai-cells = <0>;
1438 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
1446 reg = <0x30c60000 0x10000>;
1447 #sound-dai-cells = <0>;
1454 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
1462 reg = <0x30c80000 0x10000>;
1463 #sound-dai-cells = <0>;
1470 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
1478 reg = <0x30c90000 0x10000>;
1482 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
1483 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
1484 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
1485 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
1498 reg = <0x30ca0000 0x10000>;
1499 #sound-dai-cells = <0>;
1511 dmas = <&sdma2 24 25 0x80000000>;
1520 reg = <0x30e00000 0x10000>;
1531 reg = <0x30e10000 0x10000>;
1542 reg = <0x30e20000 0x10000>;
1560 reg = <0x32700000 0x100000>;
1580 reg = <0x32c00000 0x400000>;
1587 reg = <0x32e00000 0x4000>;
1599 #size-cells = <0>;
1601 port@0 {
1602 reg = <0>;
1621 reg = <0x32e30000 0x10000>;
1631 reg = <0x32e40000 0x10000>;
1647 #size-cells = <0>;
1649 port@0 {
1650 reg = <0>;
1665 reg = <0x32e50000 0x10000>;
1681 #size-cells = <0>;
1683 port@0 {
1684 reg = <0>;
1699 reg = <0x32e60000 0x400>;
1715 #size-cells = <0>;
1717 port@0 {
1718 reg = <0>;
1729 reg = <0x32e80000 0x10000>;
1747 reg = <0x32e90000 0x10000>;
1766 reg = <0x32ec0000 0x10000>;
1816 <0>, <0>, <1039500000>;
1821 reg = <0x5c 0x4>, <0x128 0x4>;
1831 #size-cells = <0>;
1833 port@0 {
1834 reg = <0>;
1860 reg = <0x32f00000 0x10000>;
1865 #phy-cells = <0>;
1871 reg = <0x32f10000 0x24>;
1886 #clock-cells = <0>;
1892 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1904 bus-range = <0x00 0xff>;
1905 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1906 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1912 interrupt-map-mask = <0 0 0 0x7>;
1913 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1914 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1915 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1916 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1918 linux,pci-domain = <0>;
1930 reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
1956 reg = <0x38000000 0x8000>;
1973 reg = <0x38008000 0x8000>;
1987 reg = <0x38300000 0x10000>;
1998 reg = <0x38310000 0x10000>;
2009 reg = <0x38330000 0x100>;
2029 reg = <0x38500000 0x200000>;
2041 reg = <0x38800000 0x10000>,
2042 <0x38880000 0xc0000>;
2051 reg = <0x3d400000 0x400000>;
2057 reg = <0x3d800000 0x400000>;
2063 reg = <0x381f0040 0x40>;
2069 #phy-cells = <0>;
2075 reg = <0x32f10100 0x8>,
2076 <0x381f0000 0x20>;
2084 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2090 reg = <0x38100000 0x10000>;
2106 reg = <0x382f0040 0x40>;
2112 #phy-cells = <0>;
2118 reg = <0x32f10108 0x8>,
2119 <0x382f0000 0x20>;
2127 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2133 reg = <0x38200000 0x10000>;
2148 reg = <0x3b6e8000 0x88000>;
2151 mboxes = <&mu2 2 0>, <&mu2 2 1>,
2152 <&mu2 3 0>, <&mu2 3 1>;