Lines Matching +full:buck4 +full:- +full:supply
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
10 compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
22 /* Memory size 512 MiB..8 GiB will be filled by U-Boot */
26 reg_eth_vio: regulator-eth-vio {
27 compatible = "regulator-fixed";
29 regulator-always-on;
30 regulator-boot-on;
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
33 regulator-name = "eth_vio";
34 vin-supply = <&buck4>;
37 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
38 compatible = "regulator-fixed";
39 enable-active-high;
41 off-on-delay-us = <12000>;
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
44 regulator-max-microvolt = <3300000>;
45 regulator-min-microvolt = <3300000>;
46 regulator-name = "VDD_3V3_SD";
47 startup-delay-us = <100>;
48 vin-supply = <&buck4>;
51 reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo { /* VDD_3V3_AWO */
52 compatible = "regulator-fixed";
53 regulator-always-on;
54 regulator-min-microvolt = <3300000>;
55 regulator-max-microvolt = <3300000>;
56 regulator-name = "VDD_3P3V_AWO";
59 wlan_pwrseq: wifi-pwrseq {
60 compatible = "mmc-pwrseq-simple";
61 reset-gpios = <&ioexp 1 GPIO_ACTIVE_LOW>;
66 cpu-supply = <&buck2>;
70 cpu-supply = <&buck2>;
74 cpu-supply = <&buck2>;
78 cpu-supply = <&buck2>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_ecspi1>;
84 cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_ecspi2>;
91 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_eqos_rgmii>;
98 phy-handle = <ðphy0g>;
99 phy-mode = "rgmii-id";
103 compatible = "snps,dwmac-mdio";
104 #address-cells = <1>;
105 #size-cells = <0>;
108 ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */
109 compatible = "ethernet-phy-id0007.c110",
110 "ethernet-phy-ieee802.3-c22";
111 interrupt-parent = <&gpio3>;
113 pinctrl-0 = <&pinctrl_ethphy0>;
114 pinctrl-names = "default";
116 reset-assert-us = <1000>;
117 reset-deassert-us = <1000>;
118 reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
119 /* Non-default PHY population option. */
123 ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
124 compatible = "ethernet-phy-id0022.1642",
125 "ethernet-phy-ieee802.3-c22";
126 interrupt-parent = <&gpio3>;
128 micrel,led-mode = <0>;
129 pinctrl-0 = <&pinctrl_ethphy0>;
130 pinctrl-names = "default";
132 reset-assert-us = <1000>;
133 reset-deassert-us = <1000>;
134 reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_fec_rmii>;
144 phy-handle = <ðphy1f>;
145 phy-mode = "rmii";
146 fsl,magic-packet;
150 #address-cells = <1>;
151 #size-cells = <0>;
154 ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
155 compatible = "ethernet-phy-id0007.c110",
156 "ethernet-phy-ieee802.3-c22";
157 interrupt-parent = <&gpio4>;
159 pinctrl-0 = <&pinctrl_ethphy1>;
160 pinctrl-names = "default";
162 reset-assert-us = <1000>;
163 reset-deassert-us = <1000>;
164 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
165 /* Non-default PHY population option. */
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_flexcan1>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_flexcan2>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_flexspi>;
189 compatible = "jedec,spi-nor";
191 spi-max-frequency = <80000000>;
192 spi-tx-bus-width = <4>;
193 spi-rx-bus-width = <4>;
198 gpio-line-names =
199 "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
200 "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
206 gpio-line-names =
208 "", "", "", "DHCOM-K", "", "", "", "",
209 "", "", "", "", "DHCOM-INT", "", "", "",
214 gpio-line-names =
216 "", "", "", "", "", "", "SOM-HW0", "",
217 "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
218 "SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
222 gpio-line-names =
225 "", "", "", "SOM-HW1", "", "", "", "",
226 "", "", "", "DHCOM-D", "", "", "", "";
230 gpio-line-names =
231 "", "", "DHCOM-C", "", "", "", "", "",
233 "", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
238 clock-frequency = <100000>;
239 pinctrl-names = "default", "gpio";
240 pinctrl-0 = <&pinctrl_i2c3>;
241 pinctrl-1 = <&pinctrl_i2c3_gpio>;
242 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
243 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_tc9595>;
251 clock-names = "ref";
253 assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>,
256 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
257 assigned-clock-rates = <13000000>, <13000000>, <156000000>;
258 reset-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
262 #address-cells = <1>;
263 #size-cells = <0>;
269 data-lanes = <1 2 3 4>;
270 remote-endpoint = <&dsi_out>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_pmic>;
281 interrupt-parent = <&gpio1>;
290 buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
291 regulator-min-microvolt = <850000>;
292 regulator-max-microvolt = <1000000>;
293 regulator-ramp-delay = <3125>;
294 regulator-always-on;
295 regulator-boot-on;
299 nxp,dvs-run-voltage = <950000>;
300 nxp,dvs-standby-voltage = <850000>;
301 regulator-min-microvolt = <850000>;
302 regulator-max-microvolt = <1000000>;
303 regulator-ramp-delay = <3125>;
304 regulator-always-on;
305 regulator-boot-on;
308 buck4: BUCK4 { /* VDD_3V3 */
309 regulator-min-microvolt = <3300000>;
310 regulator-max-microvolt = <3300000>;
311 regulator-always-on;
312 regulator-boot-on;
316 regulator-min-microvolt = <1800000>;
317 regulator-max-microvolt = <1800000>;
318 regulator-always-on;
319 regulator-boot-on;
323 regulator-min-microvolt = <1100000>;
324 regulator-max-microvolt = <1100000>;
325 regulator-always-on;
326 regulator-boot-on;
330 regulator-min-microvolt = <1800000>;
331 regulator-max-microvolt = <1800000>;
332 regulator-always-on;
333 regulator-boot-on;
337 regulator-min-microvolt = <1800000>;
338 regulator-max-microvolt = <1800000>;
339 regulator-always-on;
340 regulator-boot-on;
344 regulator-min-microvolt = <3300000>;
345 regulator-max-microvolt = <3300000>;
349 regulator-min-microvolt = <1800000>;
350 regulator-max-microvolt = <3300000>;
358 interrupts-extended = <&ioexp 7 IRQ_TYPE_EDGE_FALLING>;
359 #address-cells = <1>;
360 #size-cells = <0>;
398 interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_touch>;
401 vio-supply = <&buck4>;
405 compatible = "atmel,24c32"; /* M24C32-D */
413 interrupts-extended = <&ioexp 3 IRQ_TYPE_EDGE_FALLING>;
414 wakeup-source;
418 compatible = "atmel,24c32"; /* M24C32-D */
424 compatible = "atmel,24c32d-wl"; /* M24C32-D WL page of 0x50 */
430 compatible = "atmel,24c32d-wl"; /* M24C32-D WL page of 0x53 */
438 gpio-controller;
439 #gpio-cells = <2>;
440 interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
441 interrupt-controller;
442 #interrupt-cells = <2>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_ioexp>;
445 wakeup-source;
447 gpio-line-names =
450 "DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T",
456 clock-frequency = <100000>;
457 pinctrl-names = "default", "gpio";
458 pinctrl-0 = <&pinctrl_i2c4>;
459 pinctrl-1 = <&pinctrl_i2c4_gpio>;
460 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
461 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
466 clock-frequency = <100000>;
467 pinctrl-names = "default", "gpio";
468 pinctrl-0 = <&pinctrl_i2c5>;
469 pinctrl-1 = <&pinctrl_i2c5_gpio>;
470 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
471 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
476 samsung,burst-clock-frequency = <160000000>;
477 samsung,esc-clock-frequency = <10000000>;
484 data-lanes = <1 2 3 4>;
485 remote-endpoint = <&tc_bridge_in>;
492 pinctrl-0 = <&pinctrl_pwm1>;
493 pinctrl-names = "default";
499 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_uart1>;
502 wakeup-source;
507 pinctrl-names = "default";
508 pinctrl-0 = <&pinctrl_uart2>;
509 uart-has-rtscts;
519 assigned-clocks = <&clk IMX8MP_CLK_UART2>;
520 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
521 assigned-clock-rates = <80000000>;
524 compatible = "cypress,cyw4373a0-bt";
525 shutdown-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>;
526 max-speed = <4000000>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&pinctrl_uart3>;
533 uart-has-rtscts;
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_uart4>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&pinctrl_usb1_vbus>;
573 pinctrl-names = "default", "state_100mhz", "state_200mhz";
574 pinctrl-0 = <&pinctrl_usdhc1>;
575 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
576 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
577 mmc-pwrseq = <&wlan_pwrseq>;
578 vmmc-supply = <&buck4>;
579 bus-width = <4>;
580 non-removable;
581 cap-power-off-card;
582 keep-power-in-suspend;
585 #address-cells = <1>;
586 #size-cells = <0>;
590 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
592 * The "host-wake" interrupt output is by default not
601 pinctrl-names = "default", "state_100mhz", "state_200mhz";
602 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
603 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
604 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
605 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
606 vmmc-supply = <®_usdhc2_vmmc>;
607 bus-width = <4>;
613 pinctrl-names = "default", "state_100mhz", "state_200mhz";
614 pinctrl-0 = <&pinctrl_usdhc3>;
615 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
616 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
617 vmmc-supply = <&buck4>;
618 vqmmc-supply = <&buck5>;
619 bus-width = <8>;
620 non-removable;
625 pinctrl-names = "default";
626 pinctrl-0 = <&pinctrl_wdog>;
627 fsl,ext-reset-output;
632 pinctrl-0 = <&pinctrl_hog_base
640 pinctrl-names = "default";
642 pinctrl_dhcom_a: dhcom-a-grp {
644 /* ENET_QOS_EVENT0-OUT */
649 pinctrl_dhcom_b: dhcom-b-grp {
651 /* ENET_QOS_EVENT0-IN */
656 pinctrl_dhcom_c: dhcom-c-grp {
663 pinctrl_dhcom_d: dhcom-d-grp {
670 pinctrl_dhcom_e: dhcom-e-grp {
677 pinctrl_dhcom_f: dhcom-f-grp {
684 pinctrl_dhcom_g: dhcom-g-grp {
691 pinctrl_dhcom_h: dhcom-h-grp {
698 pinctrl_dhcom_i: dhcom-i-grp {
705 pinctrl_dhcom_j: dhcom-j-grp {
712 pinctrl_dhcom_k: dhcom-k-grp {
719 pinctrl_dhcom_l: dhcom-l-grp {
726 pinctrl_dhcom_m: dhcom-m-grp {
733 pinctrl_dhcom_n: dhcom-n-grp {
735 /* CSI2_D3- */
740 pinctrl_dhcom_o: dhcom-o-grp {
747 pinctrl_dhcom_p: dhcom-p-grp {
749 /* CSI2_D2- */
754 pinctrl_dhcom_q: dhcom-q-grp {
761 pinctrl_dhcom_r: dhcom-r-grp {
763 /* CSI2_D1- */
768 pinctrl_dhcom_s: dhcom-s-grp {
775 pinctrl_dhcom_int: dhcom-int-grp {
782 pinctrl_hog_base: dhcom-hog-base-grp {
795 pinctrl_ecspi1: dhcom-ecspi1-grp {
804 pinctrl_ecspi2: dhcom-ecspi2-grp {
813 pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp { /* RGMII */
832 pinctrl_eqos_rmii: dhcom-eqos-rmii-grp { /* RMII */
848 pinctrl_ethphy0: dhcom-ethphy0-grp {
855 pinctrl_ethphy1: dhcom-ethphy1-grp {
864 pinctrl_fec_rgmii: dhcom-fec-rgmii-grp { /* RGMII */
885 pinctrl_fec_rmii: dhcom-fec-rmii-grp { /* RMII */
901 pinctrl_flexcan1: dhcom-flexcan1-grp {
908 pinctrl_flexcan2: dhcom-flexcan2-grp {
915 pinctrl_flexspi: dhcom-flexspi-grp {
926 pinctrl_hdmi: dhcom-hdmi-grp {
933 pinctrl_i2c3: dhcom-i2c3-grp {
940 pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
947 pinctrl_i2c4: dhcom-i2c4-grp {
954 pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
961 pinctrl_i2c5: dhcom-i2c5-grp {
968 pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
975 pinctrl_ioexp: dhcom-ioexp-grp {
982 pinctrl_pmic: dhcom-pmic-grp {
989 pinctrl_pwm1: dhcom-pwm1-grp {
995 pinctrl_tc9595: dhcom-tc9595-grp {
999 /* DSI-CONV_INT Interrupt */
1004 pinctrl_sai3: dhcom-sai3-grp {
1013 pinctrl_touch: dhcom-touch-grp {
1020 pinctrl_uart1: dhcom-uart1-grp {
1030 pinctrl_uart2: dhcom-uart2-grp {
1040 pinctrl_uart3: dhcom-uart3-grp {
1049 pinctrl_uart4: dhcom-uart4-grp {
1056 pinctrl_usb1_vbus: dhcom-usb1-grp {
1063 pinctrl_usdhc1: dhcom-usdhc1-grp {
1074 pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
1085 pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
1096 pinctrl_usdhc2: dhcom-usdhc2-grp {
1108 pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
1120 pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
1132 pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
1138 pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
1144 pinctrl_usdhc3: dhcom-usdhc3-grp {
1161 pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
1178 pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
1195 pinctrl_wdog: dhcom-wdog-grp {