Lines Matching +full:0 +full:x0d0
30 pinctrl-0 = <&pinctrl_usdhc2_pwrseq>;
53 pinctrl-0 = <&pinctrl_espi2>;
59 pinctrl-0 = <&pinctrl_fec1>;
68 #size-cells = <0>;
70 ethphy0: ethernet-phy@0 {
72 reg = <0>;
83 pinctrl-0 = <&pinctrl_i2c1>;
88 reg = <0x4b>;
90 pinctrl-0 = <&pinctrl_pmic>;
95 #clock-cells = <0>;
207 pinctrl-0 = <&pinctrl_i2c3>;
214 pinctrl-0 = <&pinctrl_i2c4>;
220 pinctrl-0 = <&pinctrl_uart2>;
226 pinctrl-0 = <&pinctrl_uart3>;
235 pinctrl-0 = <&pinctrl_bluetooth>;
246 pinctrl-0 = <&pinctrl_uart4>;
258 #size-cells = <0>;
260 pinctrl-0 = <&pinctrl_usdhc2>;
272 pinctrl-0 = <&pinctrl_wlan>;
274 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
281 pinctrl-0 = <&pinctrl_wdog>;
289 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */
290 MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */
291 MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */
297 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
298 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
299 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
300 MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
306 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002
307 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002
308 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090
309 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090
310 MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090
311 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016
312 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016
313 MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016
314 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016
315 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090
316 MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016
317 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */
318 MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */
319 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */
320 MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */
326 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c2
327 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c2
333 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c2
334 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c2
340 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400000c2
341 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000c2
347 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040
353 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040
354 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040
360 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040
361 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040
362 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040
363 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040
369 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040
370 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040
376 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x090
377 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d0
378 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d0
379 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d0
380 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d0
381 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d0
387 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094
388 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4
389 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d4
390 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d4
391 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d4
392 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d4
398 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096
399 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6
400 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d6
401 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d6
402 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d6
403 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d6
409 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */
415 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x046
421 MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */
422 MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */
423 MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */
424 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */