Lines Matching +full:imx27 +full:- +full:ccm
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/imx8mm-power.h>
11 #include <dt-bindings/reset/imx8mq-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mm-pinfunc.h"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
45 #address-cells = <1>;
46 #size-cells = <0>;
48 idle-states {
49 entry-method = "psci";
51 cpu_pd_wait: cpu-pd-wait {
52 compatible = "arm,idle-state";
53 arm,psci-suspend-param = <0x0010033>;
54 local-timer-stop;
55 entry-latency-us = <1000>;
56 exit-latency-us = <700>;
57 min-residency-us = <2700>;
63 compatible = "arm,cortex-a53";
65 clock-latency = <61036>; /* two CLK32 periods */
67 enable-method = "psci";
68 i-cache-size = <0x8000>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <256>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
74 next-level-cache = <&A53_L2>;
75 operating-points-v2 = <&a53_opp_table>;
76 nvmem-cells = <&cpu_speed_grade>;
77 nvmem-cell-names = "speed_grade";
78 cpu-idle-states = <&cpu_pd_wait>;
79 #cooling-cells = <2>;
84 compatible = "arm,cortex-a53";
86 clock-latency = <61036>; /* two CLK32 periods */
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
95 next-level-cache = <&A53_L2>;
96 operating-points-v2 = <&a53_opp_table>;
97 cpu-idle-states = <&cpu_pd_wait>;
98 #cooling-cells = <2>;
103 compatible = "arm,cortex-a53";
105 clock-latency = <61036>; /* two CLK32 periods */
107 enable-method = "psci";
108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
114 next-level-cache = <&A53_L2>;
115 operating-points-v2 = <&a53_opp_table>;
116 cpu-idle-states = <&cpu_pd_wait>;
117 #cooling-cells = <2>;
122 compatible = "arm,cortex-a53";
124 clock-latency = <61036>; /* two CLK32 periods */
126 enable-method = "psci";
127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&A53_L2>;
134 operating-points-v2 = <&a53_opp_table>;
135 cpu-idle-states = <&cpu_pd_wait>;
136 #cooling-cells = <2>;
139 A53_L2: l2-cache0 {
141 cache-level = <2>;
142 cache-unified;
143 cache-size = <0x80000>;
144 cache-line-size = <64>;
145 cache-sets = <512>;
149 a53_opp_table: opp-table {
150 compatible = "operating-points-v2";
151 opp-shared;
153 opp-1200000000 {
154 opp-hz = /bits/ 64 <1200000000>;
155 opp-microvolt = <850000>;
156 opp-supported-hw = <0xe>, <0x7>;
157 clock-latency-ns = <150000>;
158 opp-suspend;
161 opp-1600000000 {
162 opp-hz = /bits/ 64 <1600000000>;
163 opp-microvolt = <950000>;
164 opp-supported-hw = <0xc>, <0x7>;
165 clock-latency-ns = <150000>;
166 opp-suspend;
169 opp-1800000000 {
170 opp-hz = /bits/ 64 <1800000000>;
171 opp-microvolt = <1000000>;
172 opp-supported-hw = <0x8>, <0x3>;
173 clock-latency-ns = <150000>;
174 opp-suspend;
178 osc_32k: clock-osc-32k {
179 compatible = "fixed-clock";
180 #clock-cells = <0>;
181 clock-frequency = <32768>;
182 clock-output-names = "osc_32k";
185 osc_24m: clock-osc-24m {
186 compatible = "fixed-clock";
187 #clock-cells = <0>;
188 clock-frequency = <24000000>;
189 clock-output-names = "osc_24m";
192 clk_ext1: clock-ext1 {
193 compatible = "fixed-clock";
194 #clock-cells = <0>;
195 clock-frequency = <133000000>;
196 clock-output-names = "clk_ext1";
199 clk_ext2: clock-ext2 {
200 compatible = "fixed-clock";
201 #clock-cells = <0>;
202 clock-frequency = <133000000>;
203 clock-output-names = "clk_ext2";
206 clk_ext3: clock-ext3 {
207 compatible = "fixed-clock";
208 #clock-cells = <0>;
209 clock-frequency = <133000000>;
210 clock-output-names = "clk_ext3";
213 clk_ext4: clock-ext4 {
214 compatible = "fixed-clock";
215 #clock-cells = <0>;
216 clock-frequency = <133000000>;
217 clock-output-names = "clk_ext4";
221 compatible = "arm,psci-1.0";
226 compatible = "arm,cortex-a53-pmu";
232 compatible = "arm,armv8-timer";
234 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
237 clock-frequency = <8000000>;
238 arm,no-tick-in-suspend;
241 thermal-zones {
242 cpu-thermal {
243 polling-delay-passive = <250>;
244 polling-delay = <2000>;
245 thermal-sensors = <&tmu>;
260 cooling-maps {
263 cooling-device =
274 #phy-cells = <0>;
275 compatible = "usb-nop-xceiv";
277 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
278 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
279 clock-names = "main_clk";
280 power-domains = <&pgc_otg1>;
284 #phy-cells = <0>;
285 compatible = "usb-nop-xceiv";
287 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
288 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
289 clock-names = "main_clk";
290 power-domains = <&pgc_otg2>;
294 compatible = "fsl,imx8mm-soc", "simple-bus";
295 #address-cells = <1>;
296 #size-cells = <1>;
298 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
299 nvmem-cells = <&imx8mm_uid>;
300 nvmem-cell-names = "soc_unique_id";
303 compatible = "fsl,aips-bus", "simple-bus";
305 #address-cells = <1>;
306 #size-cells = <1>;
309 spba2: spba-bus@30000000 {
310 compatible = "fsl,spba-bus", "simple-bus";
311 #address-cells = <1>;
312 #size-cells = <1>;
317 #sound-dai-cells = <0>;
318 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
324 clock-names = "bus", "mclk1", "mclk2", "mclk3";
326 dma-names = "rx", "tx";
331 #sound-dai-cells = <0>;
332 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
338 clock-names = "bus", "mclk1", "mclk2", "mclk3";
340 dma-names = "rx", "tx";
345 #sound-dai-cells = <0>;
346 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
352 clock-names = "bus", "mclk1", "mclk2", "mclk3";
354 dma-names = "rx", "tx";
359 #sound-dai-cells = <0>;
360 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
366 clock-names = "bus", "mclk1", "mclk2", "mclk3";
368 dma-names = "rx", "tx";
373 #sound-dai-cells = <0>;
374 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
380 clock-names = "bus", "mclk1", "mclk2", "mclk3";
382 dma-names = "rx", "tx";
386 micfil: audio-controller@30080000 {
387 compatible = "fsl,imx8mm-micfil";
398 clock-names = "ipg_clk", "ipg_clk_app",
401 dma-names = "rx";
402 #sound-dai-cells = <0>;
407 compatible = "fsl,imx35-spdif";
420 clock-names = "core", "rxtx0",
426 dma-names = "rx", "tx";
432 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
437 gpio-controller;
438 #gpio-cells = <2>;
439 interrupt-controller;
440 #interrupt-cells = <2>;
441 gpio-ranges = <&iomuxc 0 10 30>;
445 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
450 gpio-controller;
451 #gpio-cells = <2>;
452 interrupt-controller;
453 #interrupt-cells = <2>;
454 gpio-ranges = <&iomuxc 0 40 21>;
458 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
463 gpio-controller;
464 #gpio-cells = <2>;
465 interrupt-controller;
466 #interrupt-cells = <2>;
467 gpio-ranges = <&iomuxc 0 61 26>;
471 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
476 gpio-controller;
477 #gpio-cells = <2>;
478 interrupt-controller;
479 #interrupt-cells = <2>;
480 gpio-ranges = <&iomuxc 0 87 32>;
484 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
489 gpio-controller;
490 #gpio-cells = <2>;
491 interrupt-controller;
492 #interrupt-cells = <2>;
493 gpio-ranges = <&iomuxc 0 119 30>;
497 compatible = "fsl,imx8mm-tmu";
500 nvmem-cells = <&tmu_calib>;
501 nvmem-cell-names = "calib";
502 #thermal-sensor-cells = <0>;
506 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
514 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
522 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
529 sdma2: dma-controller@302c0000 {
530 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
535 clock-names = "ipg", "ahb";
536 #dma-cells = <3>;
537 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
540 sdma3: dma-controller@302b0000 {
541 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
546 clock-names = "ipg", "ahb";
547 #dma-cells = <3>;
548 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
552 compatible = "fsl,imx8mm-iomuxc";
557 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
562 compatible = "fsl,imx8mm-ocotp", "syscon";
566 #address-cells = <1>;
567 #size-cells = <1>;
582 imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
586 cpu_speed_grade: speed-grade@10 { /* 0x440 */
594 fec_mac_address: mac-address@90 { /* 0x640 */
599 anatop: clock-controller@30360000 {
600 compatible = "fsl,imx8mm-anatop";
602 #clock-cells = <1>;
606 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
609 snvs_rtc: snvs-rtc-lp {
610 compatible = "fsl,sec-v4.0-mon-rtc-lp";
616 clock-names = "snvs-rtc";
619 snvs_pwrkey: snvs-powerkey {
620 compatible = "fsl,sec-v4.0-pwrkey";
624 clock-names = "snvs-pwrkey";
626 wakeup-source;
630 snvs_lpgpr: snvs-lpgpr {
631 compatible = "fsl,imx8mm-snvs-lpgpr",
632 "fsl,imx7d-snvs-lpgpr";
636 clk: clock-controller@30380000 {
637 compatible = "fsl,imx8mm-ccm";
641 #clock-cells = <1>;
644 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
646 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
653 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
657 assigned-clock-rates = <0>, <0>, <0>,
664 src: reset-controller@30390000 {
665 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
668 #reset-cells = <1>;
672 compatible = "fsl,imx8mm-gpc";
675 interrupt-parent = <&gic>;
676 interrupt-controller;
677 #interrupt-cells = <3>;
680 #address-cells = <1>;
681 #size-cells = <0>;
683 pgc_hsiomix: power-domain@0 {
684 #power-domain-cells = <0>;
687 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
688 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
691 pgc_pcie: power-domain@1 {
692 #power-domain-cells = <0>;
694 power-domains = <&pgc_hsiomix>;
698 pgc_otg1: power-domain@2 {
699 #power-domain-cells = <0>;
703 pgc_otg2: power-domain@3 {
704 #power-domain-cells = <0>;
708 pgc_gpumix: power-domain@4 {
709 #power-domain-cells = <0>;
713 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
715 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
717 assigned-clock-rates = <800000000>, <400000000>;
720 pgc_gpu: power-domain@5 {
721 #power-domain-cells = <0>;
728 power-domains = <&pgc_gpumix>;
731 pgc_vpumix: power-domain@6 {
732 #power-domain-cells = <0>;
735 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
736 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
739 pgc_vpu_g1: power-domain@7 {
740 #power-domain-cells = <0>;
744 pgc_vpu_g2: power-domain@8 {
745 #power-domain-cells = <0>;
749 pgc_vpu_h1: power-domain@9 {
750 #power-domain-cells = <0>;
754 pgc_dispmix: power-domain@10 {
755 #power-domain-cells = <0>;
759 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
761 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
763 assigned-clock-rates = <500000000>, <200000000>;
766 pgc_mipi: power-domain@11 {
767 #power-domain-cells = <0>;
775 compatible = "fsl,aips-bus", "simple-bus";
777 #address-cells = <1>;
778 #size-cells = <1>;
782 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
787 clock-names = "ipg", "per";
788 #pwm-cells = <3>;
793 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
798 clock-names = "ipg", "per";
799 #pwm-cells = <3>;
804 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
809 clock-names = "ipg", "per";
810 #pwm-cells = <3>;
815 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
820 clock-names = "ipg", "per";
821 #pwm-cells = <3>;
826 compatible = "nxp,sysctr-timer";
830 clock-names = "per";
835 compatible = "fsl,aips-bus", "simple-bus";
837 #address-cells = <1>;
838 #size-cells = <1>;
842 spba1: spba-bus@30800000 {
843 compatible = "fsl,spba-bus", "simple-bus";
844 #address-cells = <1>;
845 #size-cells = <1>;
850 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
851 #address-cells = <1>;
852 #size-cells = <0>;
857 clock-names = "ipg", "per";
859 dma-names = "rx", "tx";
864 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
865 #address-cells = <1>;
866 #size-cells = <0>;
871 clock-names = "ipg", "per";
873 dma-names = "rx", "tx";
878 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
879 #address-cells = <1>;
880 #size-cells = <0>;
885 clock-names = "ipg", "per";
887 dma-names = "rx", "tx";
892 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
897 clock-names = "ipg", "per";
899 dma-names = "rx", "tx";
904 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
909 clock-names = "ipg", "per";
911 dma-names = "rx", "tx";
916 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
921 clock-names = "ipg", "per";
927 compatible = "fsl,sec-v4.0";
928 #address-cells = <1>;
929 #size-cells = <1>;
935 clock-names = "aclk", "ipg";
938 compatible = "fsl,sec-v4.0-job-ring";
945 compatible = "fsl,sec-v4.0-job-ring";
951 compatible = "fsl,sec-v4.0-job-ring";
958 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
959 #address-cells = <1>;
960 #size-cells = <0>;
968 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
969 #address-cells = <1>;
970 #size-cells = <0>;
978 #address-cells = <1>;
979 #size-cells = <0>;
980 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
988 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
989 #address-cells = <1>;
990 #size-cells = <0>;
998 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
1003 clock-names = "ipg", "per";
1005 dma-names = "rx", "tx";
1010 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
1014 #mbox-cells = <2>;
1018 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1024 clock-names = "ipg", "ahb", "per";
1025 fsl,tuning-start-tap = <20>;
1026 fsl,tuning-step = <2>;
1027 bus-width = <4>;
1032 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1038 clock-names = "ipg", "ahb", "per";
1039 fsl,tuning-start-tap = <20>;
1040 fsl,tuning-step = <2>;
1041 bus-width = <4>;
1046 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1052 clock-names = "ipg", "ahb", "per";
1053 fsl,tuning-start-tap = <20>;
1054 fsl,tuning-step = <2>;
1055 bus-width = <4>;
1060 #address-cells = <1>;
1061 #size-cells = <0>;
1062 compatible = "nxp,imx8mm-fspi";
1064 reg-names = "fspi_base", "fspi_mmap";
1068 clock-names = "fspi_en", "fspi";
1072 sdma1: dma-controller@30bd0000 {
1073 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
1078 clock-names = "ipg", "ahb";
1079 #dma-cells = <3>;
1080 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1084 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1095 clock-names = "ipg", "ahb", "ptp",
1097 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
1101 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1105 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1106 fsl,num-tx-queues = <3>;
1107 fsl,num-rx-queues = <3>;
1108 nvmem-cells = <&fec_mac_address>;
1109 nvmem-cell-names = "mac-address";
1110 fsl,stop-mode = <&gpr 0x10 3>;
1117 compatible = "fsl,aips-bus", "simple-bus";
1119 #address-cells = <1>;
1120 #size-cells = <1>;
1124 compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
1129 clock-names = "pix", "axi", "disp_axi";
1130 assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
1133 assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
1136 assigned-clock-rates = <24000000>, <500000000>, <200000000>;
1138 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
1143 remote-endpoint = <&dsim_from_lcdif>;
1149 compatible = "fsl,imx8mm-mipi-dsim";
1153 clock-names = "bus_clk", "sclk_mipi";
1154 assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>;
1155 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>;
1157 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1168 remote-endpoint = <&lcdif_to_dsim>;
1175 compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
1179 clock-names = "mclk";
1180 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
1185 remote-endpoint = <&imx8mm_mipi_csi_out>;
1190 disp_blk_ctrl: blk-ctrl@32e28000 {
1191 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
1193 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1196 power-domain-names = "bus", "csi-bridge",
1197 "lcdif", "mipi-dsi",
1198 "mipi-csi";
1209 clock-names = "csi-bridge-axi","csi-bridge-apb",
1210 "csi-bridge-core", "lcdif-axi",
1211 "lcdif-apb", "lcdif-pix",
1212 "dsi-pclk", "dsi-ref",
1213 "csi-aclk", "csi-pclk";
1214 #power-domain-cells = <1>;
1217 mipi_csi: mipi-csi@32e30000 {
1218 compatible = "fsl,imx8mm-mipi-csi2";
1221 assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;
1222 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;
1224 clock-frequency = <333000000>;
1229 clock-names = "pclk", "wrap", "phy", "axi";
1230 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
1234 #address-cells = <1>;
1235 #size-cells = <0>;
1245 remote-endpoint = <&csi_in>;
1252 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1256 clock-names = "usb1_ctrl_root_clk";
1257 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1258 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1261 power-domains = <&pgc_hsiomix>;
1266 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
1267 "fsl,imx6q-usbmisc";
1268 #index-cells = <1>;
1273 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1277 clock-names = "usb1_ctrl_root_clk";
1278 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1279 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1282 power-domains = <&pgc_hsiomix>;
1287 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
1288 "fsl,imx6q-usbmisc";
1289 #index-cells = <1>;
1293 pcie_phy: pcie-phy@32f00000 {
1294 compatible = "fsl,imx8mm-pcie-phy";
1297 clock-names = "ref";
1298 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1299 assigned-clock-rates = <100000000>;
1300 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
1302 reset-names = "pciephy";
1303 #phy-cells = <0>;
1308 dma_apbh: dma-controller@33000000 {
1309 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1315 #dma-cells = <1>;
1316 dma-channels = <4>;
1320 gpmi: nand-controller@33002000 {
1321 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1322 #address-cells = <1>;
1323 #size-cells = <0>;
1325 reg-names = "gpmi-nand", "bch";
1327 interrupt-names = "bch";
1330 clock-names = "gpmi_io", "gpmi_bch_apb";
1332 dma-names = "rx-tx";
1337 compatible = "fsl,imx8mm-pcie";
1339 reg-names = "dbi", "config";
1340 #address-cells = <3>;
1341 #size-cells = <2>;
1343 bus-range = <0x00 0xff>;
1345 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1346 num-lanes = <1>;
1347 num-viewport = <4>;
1349 interrupt-names = "msi";
1350 #interrupt-cells = <1>;
1351 interrupt-map-mask = <0 0 0 0x7>;
1352 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1356 fsl,max-link-speed = <2>;
1357 linux,pci-domain = <0>;
1361 clock-names = "pcie", "pcie_bus", "pcie_aux";
1362 power-domains = <&pgc_pcie>;
1365 reset-names = "apps", "turnoff";
1367 phy-names = "pcie-phy";
1371 pcie0_ep: pcie-ep@33800000 {
1372 compatible = "fsl,imx8mm-pcie-ep";
1375 reg-names = "dbi", "addr_space";
1376 num-lanes = <1>;
1378 interrupt-names = "dma";
1379 fsl,max-link-speed = <2>;
1383 clock-names = "pcie", "pcie_bus", "pcie_aux";
1384 power-domains = <&pgc_pcie>;
1387 reset-names = "apps", "turnoff";
1389 phy-names = "pcie-phy";
1390 num-ib-windows = <4>;
1391 num-ob-windows = <4>;
1403 clock-names = "reg", "bus", "core", "shader";
1404 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
1406 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1407 assigned-clock-rates = <0>, <800000000>;
1408 power-domains = <&pgc_gpu>;
1418 clock-names = "reg", "bus", "core";
1419 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
1421 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1422 assigned-clock-rates = <0>, <800000000>;
1423 power-domains = <&pgc_gpu>;
1426 vpu_g1: video-codec@38300000 {
1427 compatible = "nxp,imx8mm-vpu-g1";
1431 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
1434 vpu_g2: video-codec@38310000 {
1435 compatible = "nxp,imx8mq-vpu-g2";
1439 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
1442 vpu_blk_ctrl: blk-ctrl@38330000 {
1443 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
1445 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1447 power-domain-names = "bus", "g1", "g2", "h1";
1451 clock-names = "g1", "g2", "h1";
1452 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
1454 assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
1456 assigned-clock-rates = <600000000>,
1458 #power-domain-cells = <1>;
1461 gic: interrupt-controller@38800000 {
1462 compatible = "arm,gic-v3";
1465 #interrupt-cells = <3>;
1466 interrupt-controller;
1470 ddrc: memory-controller@3d400000 {
1471 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1473 clock-names = "core", "pll", "alt", "apb";
1480 ddr-pmu@3d800000 {
1481 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";