Lines Matching +full:0 +full:x30260000
46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
108 i-cache-size = <0x8000>;
111 d-cache-size = <0x8000>;
123 reg = <0x3>;
127 i-cache-size = <0x8000>;
130 d-cache-size = <0x8000>;
143 cache-size = <0x80000>;
156 opp-supported-hw = <0xe>, <0x7>;
164 opp-supported-hw = <0xc>, <0x7>;
172 opp-supported-hw = <0x8>, <0x3>;
180 #clock-cells = <0>;
187 #clock-cells = <0>;
194 #clock-cells = <0>;
201 #clock-cells = <0>;
208 #clock-cells = <0>;
215 #clock-cells = <0>;
274 #phy-cells = <0>;
284 #phy-cells = <0>;
293 soc: soc@0 {
297 ranges = <0x0 0x0 0x0 0x3e000000>;
298 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
304 reg = <0x30000000 0x400000>;
307 ranges = <0x30000000 0x30000000 0x400000>;
313 reg = <0x30000000 0x100000>;
317 #sound-dai-cells = <0>;
319 reg = <0x30010000 0x10000>;
325 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
331 #sound-dai-cells = <0>;
333 reg = <0x30020000 0x10000>;
339 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
345 #sound-dai-cells = <0>;
347 reg = <0x30030000 0x10000>;
353 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
359 #sound-dai-cells = <0>;
361 reg = <0x30050000 0x10000>;
367 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
373 #sound-dai-cells = <0>;
375 reg = <0x30060000 0x10000>;
381 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
388 reg = <0x30080000 0x10000>;
400 dmas = <&sdma2 24 25 0x80000000>;
402 #sound-dai-cells = <0>;
408 reg = <0x30090000 0x10000>;
425 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
433 reg = <0x30200000 0x10000>;
441 gpio-ranges = <&iomuxc 0 10 30>;
446 reg = <0x30210000 0x10000>;
454 gpio-ranges = <&iomuxc 0 40 21>;
459 reg = <0x30220000 0x10000>;
467 gpio-ranges = <&iomuxc 0 61 26>;
472 reg = <0x30230000 0x10000>;
480 gpio-ranges = <&iomuxc 0 87 32>;
485 reg = <0x30240000 0x10000>;
493 gpio-ranges = <&iomuxc 0 119 30>;
498 reg = <0x30260000 0x10000>;
502 #thermal-sensor-cells = <0>;
507 reg = <0x30280000 0x10000>;
515 reg = <0x30290000 0x10000>;
523 reg = <0x302a0000 0x10000>;
531 reg = <0x302c0000 0x10000>;
542 reg = <0x302b0000 0x10000>;
553 reg = <0x30330000 0x10000>;
558 reg = <0x30340000 0x10000>;
563 reg = <0x30350000 0x10000>;
575 * Fuse Address = (ADDR * 4) + 0x400
578 * +0x10 in Fusemap Description Table (e.g.
579 * reg = <0x4 0x8> describes fuses 0x410 and
580 * 0x420).
582 imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
583 reg = <0x4 0x8>;
586 cpu_speed_grade: speed-grade@10 { /* 0x440 */
587 reg = <0x10 4>;
590 tmu_calib: calib@3c { /* 0x4f0 */
591 reg = <0x3c 4>;
594 fec_mac_address: mac-address@90 { /* 0x640 */
595 reg = <0x90 6>;
601 reg = <0x30360000 0x10000>;
606 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
607 reg = <0x30370000 0x10000>;
610 compatible = "fsl,sec-v4.0-mon-rtc-lp";
612 offset = <0x34>;
620 compatible = "fsl,sec-v4.0-pwrkey";
638 reg = <0x30380000 0x10000>;
657 assigned-clock-rates = <0>, <0>, <0>,
666 reg = <0x30390000 0x10000>;
673 reg = <0x303a0000 0x10000>;
681 #size-cells = <0>;
683 pgc_hsiomix: power-domain@0 {
684 #power-domain-cells = <0>;
692 #power-domain-cells = <0>;
699 #power-domain-cells = <0>;
704 #power-domain-cells = <0>;
709 #power-domain-cells = <0>;
721 #power-domain-cells = <0>;
732 #power-domain-cells = <0>;
740 #power-domain-cells = <0>;
745 #power-domain-cells = <0>;
750 #power-domain-cells = <0>;
755 #power-domain-cells = <0>;
767 #power-domain-cells = <0>;
776 reg = <0x30400000 0x400000>;
779 ranges = <0x30400000 0x30400000 0x400000>;
783 reg = <0x30660000 0x10000>;
794 reg = <0x30670000 0x10000>;
805 reg = <0x30680000 0x10000>;
816 reg = <0x30690000 0x10000>;
827 reg = <0x306a0000 0x20000>;
836 reg = <0x30800000 0x400000>;
839 ranges = <0x30800000 0x30800000 0x400000>,
840 <0x8000000 0x8000000 0x10000000>;
846 reg = <0x30800000 0x100000>;
852 #size-cells = <0>;
853 reg = <0x30820000 0x10000>;
858 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
866 #size-cells = <0>;
867 reg = <0x30830000 0x10000>;
880 #size-cells = <0>;
881 reg = <0x30840000 0x10000>;
893 reg = <0x30860000 0x10000>;
898 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
905 reg = <0x30880000 0x10000>;
910 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
917 reg = <0x30890000 0x10000>;
927 compatible = "fsl,sec-v4.0";
930 reg = <0x30900000 0x40000>;
931 ranges = <0 0x30900000 0x40000>;
938 compatible = "fsl,sec-v4.0-job-ring";
939 reg = <0x1000 0x1000>;
945 compatible = "fsl,sec-v4.0-job-ring";
946 reg = <0x2000 0x1000>;
951 compatible = "fsl,sec-v4.0-job-ring";
952 reg = <0x3000 0x1000>;
960 #size-cells = <0>;
961 reg = <0x30a20000 0x10000>;
970 #size-cells = <0>;
971 reg = <0x30a30000 0x10000>;
979 #size-cells = <0>;
981 reg = <0x30a40000 0x10000>;
990 #size-cells = <0>;
991 reg = <0x30a50000 0x10000>;
999 reg = <0x30a60000 0x10000>;
1004 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1011 reg = <0x30aa0000 0x10000>;
1019 reg = <0x30b40000 0x10000>;
1033 reg = <0x30b50000 0x10000>;
1047 reg = <0x30b60000 0x10000>;
1061 #size-cells = <0>;
1063 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1074 reg = <0x30bd0000 0x10000>;
1085 reg = <0x30be0000 0x10000>;
1105 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1110 fsl,stop-mode = <&gpr 0x10 3>;
1118 reg = <0x32c00000 0x400000>;
1121 ranges = <0x32c00000 0x32c00000 0x400000>;
1125 reg = <0x32e00000 0x10000>;
1150 reg = <0x32e10000 0x400>;
1162 #size-cells = <0>;
1164 port@0 {
1165 reg = <0>;
1176 reg = <0x32e20000 0x1000>;
1192 reg = <0x32e28000 0x100>;
1219 reg = <0x32e30000 0x1000>;
1235 #size-cells = <0>;
1237 port@0 {
1238 reg = <0>;
1253 reg = <0x32e40000 0x200>;
1260 fsl,usbmisc = <&usbmisc1 0>;
1269 reg = <0x32e40200 0x200>;
1274 reg = <0x32e50000 0x200>;
1281 fsl,usbmisc = <&usbmisc2 0>;
1290 reg = <0x32e50200 0x200>;
1295 reg = <0x32f00000 0x10000>;
1303 #phy-cells = <0>;
1310 reg = <0x33000000 0x2000>;
1323 #size-cells = <0>;
1324 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1331 dmas = <&dma_apbh 0>;
1338 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1343 bus-range = <0x00 0xff>;
1344 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1345 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1351 interrupt-map-mask = <0 0 0 0x7>;
1352 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1353 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1354 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1355 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1357 linux,pci-domain = <0>;
1373 reg = <0x33800000 0x400000>,
1374 <0x18000000 0x8000000>;
1397 reg = <0x38000000 0x8000>;
1407 assigned-clock-rates = <0>, <800000000>;
1413 reg = <0x38008000 0x8000>;
1422 assigned-clock-rates = <0>, <800000000>;
1428 reg = <0x38300000 0x10000>;
1436 reg = <0x38310000 0x10000>;
1444 reg = <0x38330000 0x100>;
1463 reg = <0x38800000 0x10000>, /* GIC Dist */
1464 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
1472 reg = <0x3d400000 0x400000>;
1482 reg = <0x3d800000 0x400000>;