Lines Matching +full:gain +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
7 #include <dt-bindings/pwm/pwm.h>
12 stdout-path = &uart1;
21 compatible = "pwm-backlight";
22 brightness-levels = <0 45 63 88 119 158 203 255>;
23 default-brightness-level = <4>;
25 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
28 power-supply = <®_3p3v>;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <40000000>;
41 gpio-keys {
42 compatible = "gpio-keys";
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_gpio_keys>;
46 key-wakeup {
47 debounce-interval = <10>;
49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
50 label = "Wake-Up";
52 wakeup-source;
56 hdmi_connector: hdmi-connector {
57 compatible = "hdmi-connector";
58 ddc-i2c-bus = <&i2c2>;
60 hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>;
68 panel_lvds: panel-lvds {
69 compatible = "panel-lvds";
71 data-mapping = "vesa-24";
76 reg_1p8v: regulator-1p8v {
77 compatible = "regulator-fixed";
78 regulator-max-microvolt = <1800000>;
79 regulator-min-microvolt = <1800000>;
80 regulator-name = "+V1.8_SW";
83 reg_3p3v: regulator-3p3v {
84 compatible = "regulator-fixed";
85 regulator-max-microvolt = <3300000>;
86 regulator-min-microvolt = <3300000>;
87 regulator-name = "+V3.3_SW";
90 reg_5p0v: regulator-5p0v {
91 compatible = "regulator-fixed";
92 regulator-max-microvolt = <5000000>;
93 regulator-min-microvolt = <5000000>;
94 regulator-name = "+V5_SW";
97 /* Non PMIC On-module Supplies */
98 reg_ethphy: regulator-ethphy {
99 compatible = "regulator-fixed";
100 enable-active-high;
102 off-on-delay-us = <500000>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_reg_eth>;
105 regulator-always-on;
106 regulator-boot-on;
107 regulator-max-microvolt = <3300000>;
108 regulator-min-microvolt = <3300000>;
109 regulator-name = "On-module +V3.3_ETH";
110 startup-delay-us = <200000>;
113 reg_usb_otg1_vbus: regulator-usb-otg1 {
114 compatible = "regulator-fixed";
115 enable-active-high;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_reg_usb1_en>;
120 regulator-max-microvolt = <5000000>;
121 regulator-min-microvolt = <5000000>;
122 regulator-name = "USB_1_EN";
125 reg_usb_otg2_vbus: regulator-usb-otg2 {
126 compatible = "regulator-fixed";
127 enable-active-high;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_reg_usb2_en>;
132 regulator-max-microvolt = <5000000>;
133 regulator-min-microvolt = <5000000>;
134 regulator-name = "USB_2_EN";
137 reg_usdhc2_vmmc: regulator-usdhc2 {
138 compatible = "regulator-fixed";
139 enable-active-high;
142 off-on-delay-us = <100000>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
145 regulator-max-microvolt = <3300000>;
146 regulator-min-microvolt = <3300000>;
147 regulator-name = "+V3.3_SD";
148 startup-delay-us = <2000>;
151 reserved-memory {
152 #address-cells = <2>;
153 #size-cells = <2>;
157 /delete-node/ linux,cma;
162 cpu-supply = <®_vdd_arm>;
166 cpu-supply = <®_vdd_arm>;
170 cpu-supply = <®_vdd_arm>;
174 cpu-supply = <®_vdd_arm>;
186 operating-points-v2 = <&ddrc_opp_table>;
188 ddrc_opp_table: opp-table {
189 compatible = "operating-points-v2";
191 opp-25000000 {
192 opp-hz = /bits/ 64 <25000000>;
195 opp-100000000 {
196 opp-hz = /bits/ 64 <100000000>;
199 opp-750000000 {
200 opp-hz = /bits/ 64 <750000000>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_ecspi2>;
214 /* Verdin CAN_1 (On-module) */
216 #address-cells = <1>;
217 #size-cells = <0>;
218 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_ecspi3>;
226 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_can1_int>;
230 spi-max-frequency = <8500000>;
234 /* Verdin ETH_1 (On-module PHY) */
236 fsl,magic-packet;
237 phy-handle = <ðphy0>;
238 phy-mode = "rgmii-id";
239 phy-supply = <®_ethphy>;
240 pinctrl-names = "default", "sleep";
241 pinctrl-0 = <&pinctrl_fec1>;
242 pinctrl-1 = <&pinctrl_fec1_sleep>;
245 #address-cells = <1>;
246 #size-cells = <0>;
248 ethphy0: ethernet-phy@7 {
249 compatible = "ethernet-phy-ieee802.3-c22";
250 interrupt-parent = <&gpio1>;
252 micrel,led-mode = <0>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_flexspi0>;
265 gpio-line-names = "SODIMM_216",
284 gpio-line-names = "",
306 gpio-line-names = "SODIMM_131",
337 ctrl-sleep-moci-hog {
338 gpio-hog;
340 gpios = <1 GPIO_ACTIVE_HIGH>;
341 line-name = "CTRL_SLEEP_MOCI#";
342 output-high;
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
348 /* On-module I2C */
350 clock-frequency = <400000>;
351 pinctrl-names = "default", "gpio";
352 pinctrl-0 = <&pinctrl_i2c1>;
353 pinctrl-1 = <&pinctrl_i2c1_gpio>;
354 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
355 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
360 interrupt-parent = <&gpio1>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_pmic>;
374 nxp,dvs-run-voltage = <850000>;
375 nxp,dvs-standby-voltage = <800000>;
376 regulator-always-on;
377 regulator-boot-on;
378 regulator-max-microvolt = <850000>;
379 regulator-min-microvolt = <800000>;
380 regulator-name = "On-module +VDD_SOC (BUCK1)";
381 regulator-ramp-delay = <3125>;
385 nxp,dvs-run-voltage = <950000>;
386 nxp,dvs-standby-voltage = <850000>;
387 regulator-always-on;
388 regulator-boot-on;
389 regulator-max-microvolt = <1050000>;
390 regulator-min-microvolt = <805000>;
391 regulator-name = "On-module +VDD_ARM (BUCK2)";
392 regulator-ramp-delay = <3125>;
396 regulator-always-on;
397 regulator-boot-on;
398 regulator-max-microvolt = <1000000>;
399 regulator-min-microvolt = <805000>;
400 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
404 regulator-always-on;
405 regulator-boot-on;
406 regulator-max-microvolt = <3300000>;
407 regulator-min-microvolt = <3300000>;
408 regulator-name = "On-module +V3.3 (BUCK4)";
412 regulator-always-on;
413 regulator-boot-on;
414 regulator-max-microvolt = <1800000>;
415 regulator-min-microvolt = <1800000>;
416 regulator-name = "PWR_1V8_MOCI (BUCK5)";
420 regulator-always-on;
421 regulator-boot-on;
422 regulator-max-microvolt = <1100000>;
423 regulator-min-microvolt = <1100000>;
424 regulator-name = "On-module +VDD_DDR (BUCK6)";
428 regulator-always-on;
429 regulator-boot-on;
430 regulator-max-microvolt = <1800000>;
431 regulator-min-microvolt = <1800000>;
432 regulator-name = "On-module +V1.8_SNVS (LDO1)";
436 regulator-always-on;
437 regulator-boot-on;
438 regulator-max-microvolt = <800000>;
439 regulator-min-microvolt = <800000>;
440 regulator-name = "On-module +V0.8_SNVS (LDO2)";
444 regulator-always-on;
445 regulator-boot-on;
446 regulator-max-microvolt = <1800000>;
447 regulator-min-microvolt = <1800000>;
448 regulator-name = "On-module +V1.8A (LDO3)";
452 regulator-always-on;
453 regulator-boot-on;
454 regulator-max-microvolt = <900000>;
455 regulator-min-microvolt = <900000>;
456 regulator-name = "On-module +V0.9_MIPI (LDO4)";
460 regulator-max-microvolt = <3300000>;
461 regulator-min-microvolt = <1800000>;
462 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
475 #address-cells = <1>;
476 #size-cells = <0>;
478 /* Verdin I2C_1 (ADC_4 - ADC_3) */
482 ti,gain = <2>;
485 /* Verdin I2C_1 (ADC_4 - ADC_1) */
489 ti,gain = <2>;
492 /* Verdin I2C_1 (ADC_3 - ADC_1) */
496 ti,gain = <2>;
499 /* Verdin I2C_1 (ADC_2 - ADC_1) */
503 ti,gain = <2>;
510 ti,gain = <2>;
517 ti,gain = <2>;
524 ti,gain = <2>;
531 ti,gain = <2>;
544 clock-frequency = <10000>;
545 pinctrl-names = "default", "gpio";
546 pinctrl-0 = <&pinctrl_i2c2>;
547 pinctrl-1 = <&pinctrl_i2c2_gpio>;
548 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
549 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
557 clock-frequency = <400000>;
558 pinctrl-names = "default", "gpio";
559 pinctrl-0 = <&pinctrl_i2c3>;
560 pinctrl-1 = <&pinctrl_i2c3_gpio>;
561 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
562 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
567 clock-frequency = <400000>;
568 pinctrl-names = "default", "gpio";
569 pinctrl-0 = <&pinctrl_i2c4>;
570 pinctrl-1 = <&pinctrl_i2c4_gpio>;
571 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
572 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
574 gpio_expander_21: gpio-expander@21 {
576 #gpio-cells = <2>;
577 gpio-controller;
579 vcc-supply = <®_3p3v>;
587 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
598 shunt-resistor = <10000>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
609 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
619 interrupt-parent = <&gpio3>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
625 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
655 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
657 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
659 assigned-clock-rates = <10000000>, <250000000>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&pinctrl_pcie0>;
663 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
668 clock-names = "ref";
669 fsl,clkreq-unsupported;
670 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
671 fsl,tx-deemph-gen1 = <0x2d>;
672 fsl,tx-deemph-gen2 = <0xf>;
677 pinctrl-names = "default";
678 pinctrl-0 = <&pinctrl_pwm_1>;
679 #pwm-cells = <3>;
684 pinctrl-names = "default";
685 pinctrl-0 = <&pinctrl_pwm_2>;
686 #pwm-cells = <3>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&pinctrl_pwm_3>;
693 #pwm-cells = <3>;
698 #sound-dai-cells = <0>;
699 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
700 assigned-clock-rates = <24576000>;
701 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
702 pinctrl-names = "default";
703 pinctrl-0 = <&pinctrl_sai2>;
712 pinctrl-names = "default";
713 pinctrl-0 = <&pinctrl_uart1>;
718 pinctrl-names = "default";
719 pinctrl-0 = <&pinctrl_uart2>;
720 uart-has-rtscts;
725 pinctrl-names = "default";
726 pinctrl-0 = <&pinctrl_uart3>;
727 uart-has-rtscts;
732 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
735 pinctrl-names = "default";
736 pinctrl-0 = <&pinctrl_uart4>;
741 adp-disable;
743 hnp-disable;
744 samsung,picophy-dc-vol-level-adjust = <7>;
745 samsung,picophy-pre-emp-curr-control = <3>;
746 srp-disable;
747 vbus-supply = <®_usb_otg1_vbus>;
753 samsung,picophy-dc-vol-level-adjust = <7>;
754 samsung,picophy-pre-emp-curr-control = <3>;
755 vbus-supply = <®_usb_otg2_vbus>;
759 vcc-supply = <®_vdd_3v3>;
763 power-domains = <&pgc_otg2>;
764 vcc-supply = <®_vdd_3v3>;
767 /* On-module eMMC */
769 bus-width = <8>;
770 keep-power-in-suspend;
771 non-removable;
772 pinctrl-names = "default", "state_100mhz", "state_200mhz";
773 pinctrl-0 = <&pinctrl_usdhc1>;
774 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
775 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
781 bus-width = <4>;
782 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
783 disable-wp;
784 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
785 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
786 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
787 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
788 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
789 vmmc-supply = <®_usdhc2_vmmc>;
793 fsl,ext-reset-output;
794 pinctrl-names = "default";
795 pinctrl-0 = <&pinctrl_wdog>;
800 pinctrl-names = "default";
801 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
858 pinctrl_fec1_sleep: fec1-sleepgrp {
929 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
935 /* Verdin GPIO_10_DSI (pulled-up as active-low) */
976 /* On-module I2C */
1068 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
1165 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1181 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1213 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
1214 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
1227 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1238 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1262 * On-module Wi-Fi/BT or type specific SDHC interface
1275 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1285 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {