Lines Matching +full:0 +full:x1d0
19 reg = <0x0 0x40000000 0 0x80000000>;
25 pinctrl-0 = <&pinctrl_reg_eth_phy>;
72 pinctrl-0 = <&pinctrl_ecspi1>;
74 <&gpio1 0 GPIO_ACTIVE_LOW>;
80 touchscreen@0 {
81 reg = <0>;
84 pinctrl-0 = <&pinctrl_restouch>;
108 pinctrl-0 = <&pinctrl_fec1>;
117 #size-cells = <0>;
132 pinctrl-0 = <&pinctrl_i2c1>;
137 reg = <0x4b>;
139 pinctrl-0 = <&pinctrl_pmic>;
144 #clock-cells = <0>;
253 pinctrl-0 = <&pinctrl_i2c3>;
259 reg = <0x1a>;
271 pinctrl-0 = <&pinctrl_uart2>;
281 pinctrl-0 = <&pinctrl_uart4>;
300 #size-cells = <0>;
302 pinctrl-0 = <&pinctrl_usdhc1>;
321 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
335 pinctrl-0 = <&pinctrl_usdhc3>;
345 pinctrl-0 = <&pinctrl_wdog>;
353 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
354 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
355 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
356 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13
357 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
363 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
364 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
365 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
366 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
367 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
368 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
369 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
370 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
371 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
372 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
373 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
374 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
375 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
376 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
377 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
383 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
384 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
390 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
391 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
397 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
403 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
409 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
415 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
416 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
417 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
418 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
424 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
425 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
431 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
432 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
433 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
434 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
435 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
436 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
442 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
443 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
444 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
445 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
446 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
447 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
453 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
454 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
455 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
456 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
457 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
458 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
464 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1
470 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
471 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
472 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
473 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
474 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
475 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
476 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
482 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
483 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
484 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
485 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
486 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
487 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
488 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
494 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
495 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
496 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
497 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
498 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
499 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
500 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
506 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
507 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
508 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
509 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
510 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
511 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
512 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
513 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
514 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
515 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
516 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
522 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
523 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
524 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
525 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
526 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
527 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
528 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
529 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
530 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
531 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
532 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
538 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
539 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
540 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
541 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
542 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
543 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
544 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
545 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
546 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
547 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
548 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
554 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166