Lines Matching +full:ns +full:- +full:thermal
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
34 #address-cells = <2>;
35 #size-cells = <0>;
37 /* We have 1 clusters with 2 Cortex-A35 cores */
40 compatible = "arm,cortex-a35";
42 enable-method = "psci";
43 next-level-cache = <&A35_L2>;
45 #cooling-cells = <2>;
46 operating-points-v2 = <&a35_opp_table>;
51 compatible = "arm,cortex-a35";
53 enable-method = "psci";
54 next-level-cache = <&A35_L2>;
56 #cooling-cells = <2>;
57 operating-points-v2 = <&a35_opp_table>;
60 A35_L2: l2-cache0 {
62 cache-level = <2>;
63 cache-unified;
67 a35_opp_table: opp-table {
68 compatible = "operating-points-v2";
69 opp-shared;
71 opp-900000000 {
72 opp-hz = /bits/ 64 <900000000>;
73 opp-microvolt = <1000000>;
74 clock-latency-ns = <150000>;
77 opp-1200000000 {
78 opp-hz = /bits/ 64 <1200000000>;
79 opp-microvolt = <1100000>;
80 clock-latency-ns = <150000>;
81 opp-suspend;
85 gic: interrupt-controller@51a00000 {
86 compatible = "arm,gic-v3";
89 #interrupt-cells = <3>;
90 interrupt-controller;
94 reserved-memory {
95 #address-cells = <2>;
96 #size-cells = <2>;
101 no-map;
106 compatible = "arm,armv8-pmuv3";
111 compatible = "arm,psci-1.0";
115 system-controller {
116 compatible = "fsl,imx-scu";
117 mbox-names = "tx0",
124 pd: power-controller {
125 compatible = "fsl,imx8dl-scu-pd", "fsl,scu-pd";
126 #power-domain-cells = <1>;
129 clk: clock-controller {
130 compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
131 #clock-cells = <2>;
135 compatible = "fsl,imx8qxp-sc-gpio";
136 gpio-controller;
137 #gpio-cells = <2>;
141 compatible = "fsl,imx8dxl-iomuxc";
145 compatible = "fsl,imx8qxp-scu-ocotp";
146 #address-cells = <1>;
147 #size-cells = <1>;
159 compatible = "fsl,imx8qxp-sc-rtc";
163 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
165 wakeup-source;
169 compatible = "fsl,imx8dxl-sc-wdt", "fsl,imx-sc-wdt";
170 timeout-sec = <60>;
173 tsens: thermal-sensor {
174 compatible = "fsl,imx8dxl-sc-thermal", "fsl,imx-sc-thermal";
175 #thermal-sensor-cells = <1>;
180 compatible = "arm,armv8-timer";
182 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
187 thermal_zones: thermal-zones {
188 cpu-thermal {
189 polling-delay-passive = <250>;
190 polling-delay = <2000>;
191 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
206 cooling-maps {
209 cooling-device =
218 xtal32k: clock-xtal32k {
219 compatible = "fixed-clock";
220 #clock-cells = <0>;
221 clock-frequency = <32768>;
222 clock-output-names = "xtal_32KHz";
225 xtal24m: clock-xtal24m {
226 compatible = "fixed-clock";
227 #clock-cells = <0>;
228 clock-frequency = <24000000>;
229 clock-output-names = "xtal_24MHz";
233 #include "imx8-ss-adma.dtsi"
234 #include "imx8-ss-conn.dtsi"
235 #include "imx8-ss-ddr.dtsi"
236 #include "imx8-ss-lsio.dtsi"
239 #include "imx8dxl-ss-adma.dtsi"
240 #include "imx8dxl-ss-conn.dtsi"
241 #include "imx8dxl-ss-lsio.dtsi"
242 #include "imx8dxl-ss-ddr.dtsi"