Lines Matching +full:imx27 +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 lsio_bus_clk: clock-lsio-bus {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <100000000>;
14 clock-output-names = "lsio_bus_clk";
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
25 compatible = "fsl,imx27-pwm";
27 clock-names = "ipg", "per";
30 assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
31 assigned-clock-rates = <24000000>;
32 #pwm-cells = <3>;
38 compatible = "fsl,imx27-pwm";
40 clock-names = "ipg", "per";
43 assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
44 assigned-clock-rates = <24000000>;
45 #pwm-cells = <3>;
51 compatible = "fsl,imx27-pwm";
53 clock-names = "ipg", "per";
56 assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
57 assigned-clock-rates = <24000000>;
58 #pwm-cells = <3>;
64 compatible = "fsl,imx27-pwm";
66 clock-names = "ipg", "per";
69 assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
70 assigned-clock-rates = <24000000>;
71 #pwm-cells = <3>;
79 gpio-controller;
80 #gpio-cells = <2>;
81 interrupt-controller;
82 #interrupt-cells = <2>;
83 power-domains = <&pd IMX_SC_R_GPIO_0>;
89 gpio-controller;
90 #gpio-cells = <2>;
91 interrupt-controller;
92 #interrupt-cells = <2>;
93 power-domains = <&pd IMX_SC_R_GPIO_1>;
99 gpio-controller;
100 #gpio-cells = <2>;
101 interrupt-controller;
102 #interrupt-cells = <2>;
103 power-domains = <&pd IMX_SC_R_GPIO_2>;
109 gpio-controller;
110 #gpio-cells = <2>;
111 interrupt-controller;
112 #interrupt-cells = <2>;
113 power-domains = <&pd IMX_SC_R_GPIO_3>;
119 gpio-controller;
120 #gpio-cells = <2>;
121 interrupt-controller;
122 #interrupt-cells = <2>;
123 power-domains = <&pd IMX_SC_R_GPIO_4>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 power-domains = <&pd IMX_SC_R_GPIO_5>;
139 gpio-controller;
140 #gpio-cells = <2>;
141 interrupt-controller;
142 #interrupt-cells = <2>;
143 power-domains = <&pd IMX_SC_R_GPIO_6>;
149 gpio-controller;
150 #gpio-cells = <2>;
151 interrupt-controller;
152 #interrupt-cells = <2>;
153 power-domains = <&pd IMX_SC_R_GPIO_7>;
157 #address-cells = <1>;
158 #size-cells = <0>;
159 compatible = "nxp,imx8qxp-fspi";
161 reg-names = "fspi_base", "fspi_mmap";
165 clock-names = "fspi_en", "fspi";
166 power-domains = <&pd IMX_SC_R_FSPI_0>;
173 #mbox-cells = <2>;
180 #mbox-cells = <2>;
186 #mbox-cells = <2>;
193 #mbox-cells = <2>;
200 #mbox-cells = <2>;
207 #mbox-cells = <2>;
208 power-domains = <&pd IMX_SC_R_MU_5A>;
215 #mbox-cells = <2>;
216 power-domains = <&pd IMX_SC_R_MU_6A>;
223 #mbox-cells = <2>;
224 power-domains = <&pd IMX_SC_R_MU_13A>;
228 pwm0_lpcg: clock-controller@5d400000 {
229 compatible = "fsl,imx8qxp-lpcg";
231 #clock-cells = <1>;
237 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
240 clock-output-names = "pwm0_lpcg_ipg_clk",
245 power-domains = <&pd IMX_SC_R_PWM_0>;
248 pwm1_lpcg: clock-controller@5d410000 {
249 compatible = "fsl,imx8qxp-lpcg";
251 #clock-cells = <1>;
257 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
260 clock-output-names = "pwm1_lpcg_ipg_clk",
265 power-domains = <&pd IMX_SC_R_PWM_1>;
268 pwm2_lpcg: clock-controller@5d420000 {
269 compatible = "fsl,imx8qxp-lpcg";
271 #clock-cells = <1>;
277 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
280 clock-output-names = "pwm2_lpcg_ipg_clk",
285 power-domains = <&pd IMX_SC_R_PWM_2>;
288 pwm3_lpcg: clock-controller@5d430000 {
289 compatible = "fsl,imx8qxp-lpcg";
291 #clock-cells = <1>;
297 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
300 clock-output-names = "pwm3_lpcg_ipg_clk",
305 power-domains = <&pd IMX_SC_R_PWM_3>;
308 pwm4_lpcg: clock-controller@5d440000 {
309 compatible = "fsl,imx8qxp-lpcg";
311 #clock-cells = <1>;
317 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
320 clock-output-names = "pwm4_lpcg_ipg_clk",
325 power-domains = <&pd IMX_SC_R_PWM_4>;
328 pwm5_lpcg: clock-controller@5d450000 {
329 compatible = "fsl,imx8qxp-lpcg";
331 #clock-cells = <1>;
337 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
340 clock-output-names = "pwm5_lpcg_ipg_clk",
345 power-domains = <&pd IMX_SC_R_PWM_5>;
348 pwm6_lpcg: clock-controller@5d460000 {
349 compatible = "fsl,imx8qxp-lpcg";
351 #clock-cells = <1>;
357 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
360 clock-output-names = "pwm6_lpcg_ipg_clk",
365 power-domains = <&pd IMX_SC_R_PWM_6>;
368 pwm7_lpcg: clock-controller@5d470000 {
369 compatible = "fsl,imx8qxp-lpcg";
371 #clock-cells = <1>;
377 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
380 clock-output-names = "pwm7_lpcg_ipg_clk",
385 power-domains = <&pd IMX_SC_R_PWM_7>;