Lines Matching +full:tuning +full:- +full:step

1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 conn_axi_clk: clock-conn-axi {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <333333333>;
14 clock-output-names = "conn_axi_clk";
17 conn_ahb_clk: clock-conn-ahb {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <166666666>;
21 clock-output-names = "conn_ahb_clk";
24 conn_ipg_clk: clock-conn-ipg {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <83333333>;
28 clock-output-names = "conn_ipg_clk";
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <1>;
38 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb";
40 interrupt-parent = <&gic>;
45 ahb-burst-config = <0x0>;
46 tx-burst-size-dword = <0x10>;
47 rx-burst-size-dword = <0x10>;
48 power-domains = <&pd IMX_SC_R_USB_0>;
53 #index-cells = <1>;
54 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
59 compatible = "fsl,imx7ulp-usbphy";
62 power-domains = <&pd IMX_SC_R_USB_0_PHY>;
72 clock-names = "ipg", "ahb", "per";
73 power-domains = <&pd IMX_SC_R_SDHC_0>;
83 clock-names = "ipg", "ahb", "per";
84 power-domains = <&pd IMX_SC_R_SDHC_1>;
85 fsl,tuning-start-tap = <20>;
86 fsl,tuning-step = <2>;
96 clock-names = "ipg", "ahb", "per";
97 power-domains = <&pd IMX_SC_R_SDHC_2>;
111 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
112 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
114 assigned-clock-rates = <250000000>, <125000000>;
115 fsl,num-tx-queues = <3>;
116 fsl,num-rx-queues = <3>;
117 power-domains = <&pd IMX_SC_R_ENET_0>;
131 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
132 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
134 assigned-clock-rates = <250000000>, <125000000>;
135 fsl,num-tx-queues = <3>;
136 fsl,num-rx-queues = <3>;
137 power-domains = <&pd IMX_SC_R_ENET_1>;
142 compatible = "fsl,imx8qm-usb3";
144 #address-cells = <1>;
145 #size-cells = <1>;
152 clock-names = "lpm", "bus", "aclk", "ipg", "core";
153 assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
154 assigned-clock-rates = <250000000>;
155 power-domains = <&pd IMX_SC_R_USB_2>;
163 reg-names = "otg", "xhci", "dev";
164 interrupt-parent = <&gic>;
169 interrupt-names = "host", "peripheral", "otg", "wakeup";
171 phy-names = "cdns3,usb3-phy";
172 cdns,on-chip-buff-size = /bits/ 16 <18>;
177 usb3_phy: usb-phy@5b160000 {
178 compatible = "nxp,salvo-phy";
181 clock-names = "salvo_phy_clk";
182 power-domains = <&pd IMX_SC_R_USB_2_PHY>;
183 #phy-cells = <0>;
188 sdhc0_lpcg: clock-controller@5b200000 {
189 compatible = "fsl,imx8qxp-lpcg";
191 #clock-cells = <1>;
194 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
196 clock-output-names = "sdhc0_lpcg_per_clk",
199 power-domains = <&pd IMX_SC_R_SDHC_0>;
202 sdhc1_lpcg: clock-controller@5b210000 {
203 compatible = "fsl,imx8qxp-lpcg";
205 #clock-cells = <1>;
208 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
210 clock-output-names = "sdhc1_lpcg_per_clk",
213 power-domains = <&pd IMX_SC_R_SDHC_1>;
216 sdhc2_lpcg: clock-controller@5b220000 {
217 compatible = "fsl,imx8qxp-lpcg";
219 #clock-cells = <1>;
222 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
224 clock-output-names = "sdhc2_lpcg_per_clk",
227 power-domains = <&pd IMX_SC_R_SDHC_2>;
230 enet0_lpcg: clock-controller@5b230000 {
231 compatible = "fsl,imx8qxp-lpcg";
233 #clock-cells = <1>;
240 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
243 clock-output-names = "enet0_lpcg_timer_clk",
249 power-domains = <&pd IMX_SC_R_ENET_0>;
252 enet1_lpcg: clock-controller@5b240000 {
253 compatible = "fsl,imx8qxp-lpcg";
255 #clock-cells = <1>;
262 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
265 clock-output-names = "enet1_lpcg_timer_clk",
271 power-domains = <&pd IMX_SC_R_ENET_1>;
274 usb2_lpcg: clock-controller@5b270000 {
275 compatible = "fsl,imx8qxp-lpcg";
277 #clock-cells = <1>;
279 clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
280 clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
281 power-domains = <&pd IMX_SC_R_USB_0_PHY>;
284 usb3_lpcg: clock-controller@5b280000 {
285 compatible = "fsl,imx8qxp-lpcg";
287 #clock-cells = <1>;
288 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
297 clock-output-names = "usb3_app_clk",
303 power-domains = <&pd IMX_SC_R_USB_2_PHY>;