Lines Matching +full:imx8qxp +full:- +full:lpcg
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 audio_ipg_clk: clock-audio-ipg {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <120000000>;
14 clock-output-names = "audio_ipg_clk";
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 edma0: dma-controller@591f0000 {
24 compatible = "fsl,imx8qm-edma";
26 #dma-cells = <3>;
27 dma-channels = <24>;
28 dma-channel-mask = <0x5c0c00>;
53 power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
79 dsp_lpcg: clock-controller@59580000 {
80 compatible = "fsl,imx8qxp-lpcg";
82 #clock-cells = <1>;
86 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
88 clock-output-names = "dsp_lpcg_adb_clk",
91 power-domains = <&pd IMX_SC_R_DSP>;
94 dsp_ram_lpcg: clock-controller@59590000 {
95 compatible = "fsl,imx8qxp-lpcg";
97 #clock-cells = <1>;
99 clock-indices = <IMX_LPCG_CLK_4>;
100 clock-output-names = "dsp_ram_lpcg_ipg_clk";
101 power-domains = <&pd IMX_SC_R_DSP_RAM>;
105 compatible = "fsl,imx8qxp-dsp";
110 clock-names = "ipg", "ocram", "core";
111 power-domains = <&pd IMX_SC_R_MU_13A>,
115 mbox-names = "txdb0", "txdb1",
121 memory-region = <&dsp_reserved>;
125 edma1: dma-controller@599f0000 {
126 compatible = "fsl,imx8qm-edma";
128 #dma-cells = <3>;
129 dma-channels = <11>;
130 dma-channel-mask = <0xc0>;
142 power-domains = <&pd IMX_SC_R_DMA_1_CH0>,