Lines Matching +full:phy +full:- +full:sata3

1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 	compatible = "fsl,lx2162a-qds", "fsl,lx2160a";
23 		stdout-path = "serial0:115200n8";
26 	sb_3v3: regulator-sb3v3 {
27 		compatible = "regulator-fixed";
28 		regulator-name = "LTM4619-3.3VSB";
29 		regulator-min-microvolt = <3300000>;
30 		regulator-max-microvolt = <3300000>;
33 	mdio-mux-1 {
34 		compatible = "mdio-mux-multiplexer";
35 		mux-controls = <&mux 0>;
36 		mdio-parent-bus = <&emdio1>;
37 		#address-cells = <1>;
38 		#size-cells = <0>;
40 		mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */
42 			#address-cells = <1>;
43 			#size-cells = <0>;
45 			rgmii_phy1: ethernet-phy@1 {
46 				compatible = "ethernet-phy-id001c.c916";
48 				eee-broken-1000t;
52 		mdio@8 { /* On-board RTL8211F PHY #2 RGMII2 */
54 			#address-cells = <1>;
55 			#size-cells = <0>;
57 			rgmii_phy2: ethernet-phy@2 {
58 				compatible = "ethernet-phy-id001c.c916";
60 				eee-broken-1000t;
66 			#address-cells = <1>;
67 			#size-cells = <0>;
72 			#address-cells = <1>;
73 			#size-cells = <0>;
78 			#address-cells = <1>;
79 			#size-cells = <0>;
84 			#address-cells = <1>;
85 			#size-cells = <0>;
90 			#address-cells = <1>;
91 			#size-cells = <0>;
96 			#address-cells = <1>;
97 			#size-cells = <0>;
102 			#address-cells = <1>;
103 			#size-cells = <0>;
108 			#address-cells = <1>;
109 			#size-cells = <0>;
113 	mdio-mux-2 {
114 		compatible = "mdio-mux-multiplexer";
115 		mux-controls = <&mux 1>;
116 		mdio-parent-bus = <&emdio2>;
117 		#address-cells = <1>;
118 		#size-cells = <0>;
122 			#address-cells = <1>;
123 			#size-cells = <0>;
128 			#address-cells = <1>;
129 			#size-cells = <0>;
134 			#address-cells = <1>;
135 			#size-cells = <0>;
140 			#address-cells = <1>;
141 			#size-cells = <0>;
146 			#address-cells = <1>;
147 			#size-cells = <0>;
152 			#address-cells = <1>;
153 			#size-cells = <0>;
158 			#address-cells = <1>;
159 			#size-cells = <0>;
164 			#address-cells = <1>;
165 			#size-cells = <0>;
183 	phy-handle = <&rgmii_phy1>;
184 	phy-connection-type = "rgmii-id";
188 	phy-handle = <&rgmii_phy2>;
189 	phy-connection-type = "rgmii-id";
196 		#address-cells = <1>;
197 		#size-cells = <1>;
198 		compatible = "jedec,spi-nor";
200 		spi-max-frequency = <1000000>;
208 		#address-cells = <1>;
209 		#size-cells = <1>;
210 		compatible = "jedec,spi-nor";
212 		spi-max-frequency = <1000000>;
220 		#address-cells = <1>;
221 		#size-cells = <1>;
222 		compatible = "jedec,spi-nor";
224 		spi-max-frequency = <1000000>;
237 	sd-uhs-sdr104;
238 	sd-uhs-sdr50;
239 	sd-uhs-sdr25;
240 	sd-uhs-sdr12;
245 	mmc-hs200-1_8v;
246 	mmc-hs400-1_8v;
247 	bus-width = <8>;
255 		#address-cells = <1>;
256 		#size-cells = <1>;
257 		compatible = "jedec,spi-nor";
258 		m25p,fast-read;
259 		spi-max-frequency = <50000000>;
261 		spi-rx-bus-width = <8>;
262 		spi-tx-bus-width = <8>;
270 		compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
271 			     "simple-mfd";
274 		mux: mux-controller {
275 			compatible = "reg-mux";
276 			#mux-control-cells = <1>;
277 			mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
282 	i2c-mux@77 {
285 		#address-cells = <1>;
286 		#size-cells = <0>;
289 			#address-cells = <1>;
290 			#size-cells = <0>;
293 			power-monitor@40 {
296 				shunt-resistor = <500>;
299 			power-monitor@41 {
302 				shunt-resistor = <1000>;
307 			#address-cells = <1>;
308 			#size-cells = <0>;
311 			temperature-sensor@4c {
314 				vcc-supply = <&sb_3v3>;
320 				/* IRQ_RTC_B -> IRQ11_B(CPLD) -> IRQ11(CPU), active low */
321 				interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>;
343 &sata3 {