Lines Matching +full:smmu +full:- +full:v3
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
28 // 8 clusters having 2 Cortex-A72 cores each
31 compatible = "arm,cortex-a72";
32 enable-method = "psci";
35 d-cache-size = <0x8000>;
36 d-cache-line-size = <64>;
37 d-cache-sets = <128>;
38 i-cache-size = <0xC000>;
39 i-cache-line-size = <64>;
40 i-cache-sets = <192>;
41 next-level-cache = <&cluster0_l2>;
42 cpu-idle-states = <&cpu_pw15>;
43 #cooling-cells = <2>;
48 compatible = "arm,cortex-a72";
49 enable-method = "psci";
52 d-cache-size = <0x8000>;
53 d-cache-line-size = <64>;
54 d-cache-sets = <128>;
55 i-cache-size = <0xC000>;
56 i-cache-line-size = <64>;
57 i-cache-sets = <192>;
58 next-level-cache = <&cluster0_l2>;
59 cpu-idle-states = <&cpu_pw15>;
60 #cooling-cells = <2>;
65 compatible = "arm,cortex-a72";
66 enable-method = "psci";
69 d-cache-size = <0x8000>;
70 d-cache-line-size = <64>;
71 d-cache-sets = <128>;
72 i-cache-size = <0xC000>;
73 i-cache-line-size = <64>;
74 i-cache-sets = <192>;
75 next-level-cache = <&cluster1_l2>;
76 cpu-idle-states = <&cpu_pw15>;
77 #cooling-cells = <2>;
82 compatible = "arm,cortex-a72";
83 enable-method = "psci";
86 d-cache-size = <0x8000>;
87 d-cache-line-size = <64>;
88 d-cache-sets = <128>;
89 i-cache-size = <0xC000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <192>;
92 next-level-cache = <&cluster1_l2>;
93 cpu-idle-states = <&cpu_pw15>;
94 #cooling-cells = <2>;
99 compatible = "arm,cortex-a72";
100 enable-method = "psci";
103 d-cache-size = <0x8000>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 i-cache-size = <0xC000>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <192>;
109 next-level-cache = <&cluster2_l2>;
110 cpu-idle-states = <&cpu_pw15>;
111 #cooling-cells = <2>;
116 compatible = "arm,cortex-a72";
117 enable-method = "psci";
120 d-cache-size = <0x8000>;
121 d-cache-line-size = <64>;
122 d-cache-sets = <128>;
123 i-cache-size = <0xC000>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <192>;
126 next-level-cache = <&cluster2_l2>;
127 cpu-idle-states = <&cpu_pw15>;
128 #cooling-cells = <2>;
133 compatible = "arm,cortex-a72";
134 enable-method = "psci";
137 d-cache-size = <0x8000>;
138 d-cache-line-size = <64>;
139 d-cache-sets = <128>;
140 i-cache-size = <0xC000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <192>;
143 next-level-cache = <&cluster3_l2>;
144 cpu-idle-states = <&cpu_pw15>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a72";
151 enable-method = "psci";
154 d-cache-size = <0x8000>;
155 d-cache-line-size = <64>;
156 d-cache-sets = <128>;
157 i-cache-size = <0xC000>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <192>;
160 next-level-cache = <&cluster3_l2>;
161 cpu-idle-states = <&cpu_pw15>;
162 #cooling-cells = <2>;
167 compatible = "arm,cortex-a72";
168 enable-method = "psci";
171 d-cache-size = <0x8000>;
172 d-cache-line-size = <64>;
173 d-cache-sets = <128>;
174 i-cache-size = <0xC000>;
175 i-cache-line-size = <64>;
176 i-cache-sets = <192>;
177 next-level-cache = <&cluster4_l2>;
178 cpu-idle-states = <&cpu_pw15>;
179 #cooling-cells = <2>;
184 compatible = "arm,cortex-a72";
185 enable-method = "psci";
188 d-cache-size = <0x8000>;
189 d-cache-line-size = <64>;
190 d-cache-sets = <128>;
191 i-cache-size = <0xC000>;
192 i-cache-line-size = <64>;
193 i-cache-sets = <192>;
194 next-level-cache = <&cluster4_l2>;
195 cpu-idle-states = <&cpu_pw15>;
196 #cooling-cells = <2>;
201 compatible = "arm,cortex-a72";
202 enable-method = "psci";
205 d-cache-size = <0x8000>;
206 d-cache-line-size = <64>;
207 d-cache-sets = <128>;
208 i-cache-size = <0xC000>;
209 i-cache-line-size = <64>;
210 i-cache-sets = <192>;
211 next-level-cache = <&cluster5_l2>;
212 cpu-idle-states = <&cpu_pw15>;
213 #cooling-cells = <2>;
218 compatible = "arm,cortex-a72";
219 enable-method = "psci";
222 d-cache-size = <0x8000>;
223 d-cache-line-size = <64>;
224 d-cache-sets = <128>;
225 i-cache-size = <0xC000>;
226 i-cache-line-size = <64>;
227 i-cache-sets = <192>;
228 next-level-cache = <&cluster5_l2>;
229 cpu-idle-states = <&cpu_pw15>;
230 #cooling-cells = <2>;
235 compatible = "arm,cortex-a72";
236 enable-method = "psci";
239 d-cache-size = <0x8000>;
240 d-cache-line-size = <64>;
241 d-cache-sets = <128>;
242 i-cache-size = <0xC000>;
243 i-cache-line-size = <64>;
244 i-cache-sets = <192>;
245 next-level-cache = <&cluster6_l2>;
246 cpu-idle-states = <&cpu_pw15>;
247 #cooling-cells = <2>;
252 compatible = "arm,cortex-a72";
253 enable-method = "psci";
256 d-cache-size = <0x8000>;
257 d-cache-line-size = <64>;
258 d-cache-sets = <128>;
259 i-cache-size = <0xC000>;
260 i-cache-line-size = <64>;
261 i-cache-sets = <192>;
262 next-level-cache = <&cluster6_l2>;
263 cpu-idle-states = <&cpu_pw15>;
264 #cooling-cells = <2>;
269 compatible = "arm,cortex-a72";
270 enable-method = "psci";
273 d-cache-size = <0x8000>;
274 d-cache-line-size = <64>;
275 d-cache-sets = <128>;
276 i-cache-size = <0xC000>;
277 i-cache-line-size = <64>;
278 i-cache-sets = <192>;
279 next-level-cache = <&cluster7_l2>;
280 cpu-idle-states = <&cpu_pw15>;
281 #cooling-cells = <2>;
286 compatible = "arm,cortex-a72";
287 enable-method = "psci";
290 d-cache-size = <0x8000>;
291 d-cache-line-size = <64>;
292 d-cache-sets = <128>;
293 i-cache-size = <0xC000>;
294 i-cache-line-size = <64>;
295 i-cache-sets = <192>;
296 next-level-cache = <&cluster7_l2>;
297 cpu-idle-states = <&cpu_pw15>;
298 #cooling-cells = <2>;
301 cluster0_l2: l2-cache0 {
303 cache-unified;
304 cache-size = <0x100000>;
305 cache-line-size = <64>;
306 cache-sets = <1024>;
307 cache-level = <2>;
310 cluster1_l2: l2-cache1 {
312 cache-unified;
313 cache-size = <0x100000>;
314 cache-line-size = <64>;
315 cache-sets = <1024>;
316 cache-level = <2>;
319 cluster2_l2: l2-cache2 {
321 cache-unified;
322 cache-size = <0x100000>;
323 cache-line-size = <64>;
324 cache-sets = <1024>;
325 cache-level = <2>;
328 cluster3_l2: l2-cache3 {
330 cache-unified;
331 cache-size = <0x100000>;
332 cache-line-size = <64>;
333 cache-sets = <1024>;
334 cache-level = <2>;
337 cluster4_l2: l2-cache4 {
339 cache-unified;
340 cache-size = <0x100000>;
341 cache-line-size = <64>;
342 cache-sets = <1024>;
343 cache-level = <2>;
346 cluster5_l2: l2-cache5 {
348 cache-unified;
349 cache-size = <0x100000>;
350 cache-line-size = <64>;
351 cache-sets = <1024>;
352 cache-level = <2>;
355 cluster6_l2: l2-cache6 {
357 cache-unified;
358 cache-size = <0x100000>;
359 cache-line-size = <64>;
360 cache-sets = <1024>;
361 cache-level = <2>;
364 cluster7_l2: l2-cache7 {
366 cache-unified;
367 cache-size = <0x100000>;
368 cache-line-size = <64>;
369 cache-sets = <1024>;
370 cache-level = <2>;
373 cpu_pw15: cpu-pw15 {
374 compatible = "arm,idle-state";
375 idle-state-name = "PW15";
376 arm,psci-suspend-param = <0x0>;
377 entry-latency-us = <2000>;
378 exit-latency-us = <2000>;
379 min-residency-us = <6000>;
383 gic: interrupt-controller@6000000 {
384 compatible = "arm,gic-v3";
391 #interrupt-cells = <3>;
392 #address-cells = <2>;
393 #size-cells = <2>;
395 interrupt-controller;
398 its: msi-controller@6020000 {
399 compatible = "arm,gic-v3-its";
400 msi-controller;
406 compatible = "arm,armv8-timer";
414 compatible = "arm,cortex-a72-pmu";
419 compatible = "arm,psci-0.2";
424 // DRAM space - 1, size : 2 GB DRAM
429 ddr1: memory-controller@1080000 {
430 compatible = "fsl,qoriq-memory-controller";
433 little-endian;
436 ddr2: memory-controller@1090000 {
437 compatible = "fsl,qoriq-memory-controller";
440 little-endian;
443 // One clock unit-sysclk node which bootloader require during DT fix-up
445 compatible = "fixed-clock";
446 #clock-cells = <0>;
447 clock-frequency = <100000000>; // fixed up by bootloader
448 clock-output-names = "sysclk";
451 thermal-zones {
452 cluster6-7 {
453 polling-delay-passive = <1000>;
454 polling-delay = <5000>;
455 thermal-sensors = <&tmu 0>;
458 cluster6_7_alert: cluster6-7-alert {
464 cluster6_7_crit: cluster6-7-crit {
471 cooling-maps {
474 cooling-device =
495 ddr-cluster5 {
496 polling-delay-passive = <1000>;
497 polling-delay = <5000>;
498 thermal-sensors = <&tmu 1>;
501 ddr-cluster5-alert {
507 ddr-cluster5-crit {
516 polling-delay-passive = <1000>;
517 polling-delay = <5000>;
518 thermal-sensors = <&tmu 2>;
521 wriop-alert {
527 wriop-crit {
535 dce-qbman-hsio2 {
536 polling-delay-passive = <1000>;
537 polling-delay = <5000>;
538 thermal-sensors = <&tmu 3>;
541 dce-qbman-alert {
547 dce-qbman-crit {
555 ccn-dpaa-tbu {
556 polling-delay-passive = <1000>;
557 polling-delay = <5000>;
558 thermal-sensors = <&tmu 4>;
561 ccn-dpaa-alert {
567 ccn-dpaa-crit {
575 cluster4-hsio3 {
576 polling-delay-passive = <1000>;
577 polling-delay = <5000>;
578 thermal-sensors = <&tmu 5>;
581 clust4-hsio3-alert {
587 clust4-hsio3-crit {
595 cluster2-3 {
596 polling-delay-passive = <1000>;
597 polling-delay = <5000>;
598 thermal-sensors = <&tmu 6>;
601 cluster2-3-alert {
607 cluster2-3-crit {
617 compatible = "simple-bus";
618 #address-cells = <2>;
619 #size-cells = <2>;
621 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
624 compatible = "fsl,lynx-28g";
626 #phy-cells = <1>;
630 compatible = "fsl,lynx-28g";
632 #phy-cells = <1>;
637 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
638 fsl,sec-era = <10>;
639 #address-cells = <1>;
640 #size-cells = <1>;
644 dma-coherent;
648 compatible = "fsl,sec-v5.0-job-ring",
649 "fsl,sec-v4.0-job-ring";
655 compatible = "fsl,sec-v5.0-job-ring",
656 "fsl,sec-v4.0-job-ring";
662 compatible = "fsl,sec-v5.0-job-ring",
663 "fsl,sec-v4.0-job-ring";
669 compatible = "fsl,sec-v5.0-job-ring",
670 "fsl,sec-v4.0-job-ring";
676 clockgen: clock-controller@1300000 {
677 compatible = "fsl,lx2160a-clockgen";
679 #clock-cells = <2>;
684 compatible = "fsl,lx2160a-dcfg", "syscon";
686 little-endian;
690 compatible = "fsl,ls1028a-sfp";
694 clock-names = "sfp";
698 compatible = "fsl,lx2160a-isc", "syscon";
700 little-endian;
701 #address-cells = <1>;
702 #size-cells = <1>;
705 extirq: interrupt-controller@14 {
706 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq";
707 #interrupt-cells = <2>;
708 #address-cells = <0>;
709 interrupt-controller;
711 interrupt-map =
724 interrupt-map-mask = <0xf 0x0>;
729 compatible = "fsl,qoriq-tmu";
732 fsl,tmu-range = <0x800000e6 0x8001017d>;
733 fsl,tmu-calibration =
738 little-endian;
739 #thermal-sensor-cells = <1>;
743 compatible = "fsl,vf610-i2c";
744 #address-cells = <1>;
745 #size-cells = <0>;
748 clock-names = "i2c";
751 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
756 compatible = "fsl,vf610-i2c";
757 #address-cells = <1>;
758 #size-cells = <0>;
761 clock-names = "i2c";
768 compatible = "fsl,vf610-i2c";
769 #address-cells = <1>;
770 #size-cells = <0>;
773 clock-names = "i2c";
780 compatible = "fsl,vf610-i2c";
781 #address-cells = <1>;
782 #size-cells = <0>;
785 clock-names = "i2c";
792 compatible = "fsl,vf610-i2c";
793 #address-cells = <1>;
794 #size-cells = <0>;
797 clock-names = "i2c";
800 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
805 compatible = "fsl,vf610-i2c";
806 #address-cells = <1>;
807 #size-cells = <0>;
810 clock-names = "i2c";
817 compatible = "fsl,vf610-i2c";
818 #address-cells = <1>;
819 #size-cells = <0>;
822 clock-names = "i2c";
829 compatible = "fsl,vf610-i2c";
830 #address-cells = <1>;
831 #size-cells = <0>;
834 clock-names = "i2c";
841 compatible = "nxp,lx2160a-fspi";
842 #address-cells = <1>;
843 #size-cells = <0>;
846 reg-names = "fspi_base", "fspi_mmap";
852 clock-names = "fspi_en", "fspi";
857 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
858 #address-cells = <1>;
859 #size-cells = <0>;
864 clock-names = "dspi";
865 spi-num-chipselects = <5>;
866 bus-num = <0>;
871 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
872 #address-cells = <1>;
873 #size-cells = <0>;
878 clock-names = "dspi";
879 spi-num-chipselects = <5>;
880 bus-num = <1>;
885 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
886 #address-cells = <1>;
887 #size-cells = <0>;
892 clock-names = "dspi";
893 spi-num-chipselects = <5>;
894 bus-num = <2>;
904 dma-coherent;
905 voltage-ranges = <1800 1800 3300 3300>;
906 sdhci,auto-cmd12;
907 little-endian;
908 bus-width = <4>;
918 dma-coherent;
919 voltage-ranges = <1800 1800 3300 3300>;
920 sdhci,auto-cmd12;
921 broken-cd;
922 little-endian;
923 bus-width = <4>;
928 compatible = "fsl,lx2160ar1-flexcan";
934 clock-names = "ipg", "per";
935 fsl,clk-source = /bits/ 8 <0>;
940 compatible = "fsl,lx2160ar1-flexcan";
946 clock-names = "ipg", "per";
947 fsl,clk-source = /bits/ 8 <0>;
952 compatible = "arm,sbsa-uart","arm,pl011";
955 current-speed = <115200>;
960 compatible = "arm,sbsa-uart","arm,pl011";
963 current-speed = <115200>;
968 compatible = "arm,sbsa-uart","arm,pl011";
971 current-speed = <115200>;
976 compatible = "arm,sbsa-uart","arm,pl011";
979 current-speed = <115200>;
984 compatible = "fsl,qoriq-gpio";
987 gpio-controller;
988 little-endian;
989 #gpio-cells = <2>;
990 interrupt-controller;
991 #interrupt-cells = <2>;
995 compatible = "fsl,qoriq-gpio";
998 gpio-controller;
999 little-endian;
1000 #gpio-cells = <2>;
1001 interrupt-controller;
1002 #interrupt-cells = <2>;
1006 compatible = "fsl,qoriq-gpio";
1009 gpio-controller;
1010 little-endian;
1011 #gpio-cells = <2>;
1012 interrupt-controller;
1013 #interrupt-cells = <2>;
1017 compatible = "fsl,qoriq-gpio";
1020 gpio-controller;
1021 little-endian;
1022 #gpio-cells = <2>;
1023 interrupt-controller;
1024 #interrupt-cells = <2>;
1028 compatible = "arm,sbsa-gwdt";
1032 timeout-sec = <30>;
1035 rcpm: power-controller@1e34040 {
1036 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
1038 #fsl,rcpm-wakeup-cells = <7>;
1039 little-endian;
1043 compatible = "fsl,lx2160a-ftm-alarm";
1045 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1054 snps,quirk-frame-length-adjustment = <0x20>;
1055 usb3-lpm-capable;
1057 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1066 snps,quirk-frame-length-adjustment = <0x20>;
1067 usb3-lpm-capable;
1069 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1074 compatible = "fsl,lx2160a-ahci";
1077 reg-names = "ahci", "sata-ecc";
1081 dma-coherent;
1086 compatible = "fsl,lx2160a-ahci";
1089 reg-names = "ahci", "sata-ecc";
1093 dma-coherent;
1098 compatible = "fsl,lx2160a-ahci";
1101 reg-names = "ahci", "sata-ecc";
1105 dma-coherent;
1110 compatible = "fsl,lx2160a-ahci";
1113 reg-names = "ahci", "sata-ecc";
1117 dma-coherent;
1122 compatible = "fsl,lx2160a-pcie";
1125 reg-names = "csr_axi_slave", "config_axi_slave";
1129 interrupt-names = "aer", "pme", "intr";
1130 #address-cells = <3>;
1131 #size-cells = <2>;
1133 dma-coherent;
1134 apio-wins = <8>;
1135 ppio-wins = <8>;
1136 bus-range = <0x0 0xff>;
1137 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1138 msi-parent = <&its>;
1139 #interrupt-cells = <1>;
1140 interrupt-map-mask = <0 0 0 7>;
1141 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1145 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1150 compatible = "fsl,lx2160a-pcie";
1153 reg-names = "csr_axi_slave", "config_axi_slave";
1157 interrupt-names = "aer", "pme", "intr";
1158 #address-cells = <3>;
1159 #size-cells = <2>;
1161 dma-coherent;
1162 apio-wins = <8>;
1163 ppio-wins = <8>;
1164 bus-range = <0x0 0xff>;
1165 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1166 msi-parent = <&its>;
1167 #interrupt-cells = <1>;
1168 interrupt-map-mask = <0 0 0 7>;
1169 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1173 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1178 compatible = "fsl,lx2160a-pcie";
1181 reg-names = "csr_axi_slave", "config_axi_slave";
1185 interrupt-names = "aer", "pme", "intr";
1186 #address-cells = <3>;
1187 #size-cells = <2>;
1189 dma-coherent;
1190 apio-wins = <256>;
1191 ppio-wins = <24>;
1192 bus-range = <0x0 0xff>;
1193 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1194 msi-parent = <&its>;
1195 #interrupt-cells = <1>;
1196 interrupt-map-mask = <0 0 0 7>;
1197 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1201 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1206 compatible = "fsl,lx2160a-pcie";
1209 reg-names = "csr_axi_slave", "config_axi_slave";
1213 interrupt-names = "aer", "pme", "intr";
1214 #address-cells = <3>;
1215 #size-cells = <2>;
1217 dma-coherent;
1218 apio-wins = <8>;
1219 ppio-wins = <8>;
1220 bus-range = <0x0 0xff>;
1221 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1222 msi-parent = <&its>;
1223 #interrupt-cells = <1>;
1224 interrupt-map-mask = <0 0 0 7>;
1225 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1229 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1234 compatible = "fsl,lx2160a-pcie";
1237 reg-names = "csr_axi_slave", "config_axi_slave";
1241 interrupt-names = "aer", "pme", "intr";
1242 #address-cells = <3>;
1243 #size-cells = <2>;
1245 dma-coherent;
1246 apio-wins = <256>;
1247 ppio-wins = <24>;
1248 bus-range = <0x0 0xff>;
1249 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1250 msi-parent = <&its>;
1251 #interrupt-cells = <1>;
1252 interrupt-map-mask = <0 0 0 7>;
1253 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1257 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1262 compatible = "fsl,lx2160a-pcie";
1265 reg-names = "csr_axi_slave", "config_axi_slave";
1269 interrupt-names = "aer", "pme", "intr";
1270 #address-cells = <3>;
1271 #size-cells = <2>;
1273 dma-coherent;
1274 apio-wins = <8>;
1275 ppio-wins = <8>;
1276 bus-range = <0x0 0xff>;
1277 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1278 msi-parent = <&its>;
1279 #interrupt-cells = <1>;
1280 interrupt-map-mask = <0 0 0 7>;
1281 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1285 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1289 smmu: iommu@5000000 {
1290 compatible = "arm,mmu-500";
1292 #iommu-cells = <1>;
1293 #global-interrupts = <14>;
1298 // global non-secure fault
1300 // combined non-secure
1302 // performance counter interrupts 0-9
1378 dma-coherent;
1382 compatible = "fsl,dpaa2-console";
1386 ptp-timer@8b95000 {
1387 compatible = "fsl,dpaa2-ptp";
1391 little-endian;
1392 fsl,extts-fifo;
1395 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1397 compatible = "fsl,fman-memac-mdio";
1400 #address-cells = <1>;
1401 #size-cells = <0>;
1402 little-endian;
1403 clock-frequency = <2500000>;
1410 compatible = "fsl,fman-memac-mdio";
1413 little-endian;
1414 #address-cells = <1>;
1415 #size-cells = <0>;
1416 clock-frequency = <2500000>;
1423 compatible = "fsl,fman-memac-mdio";
1425 little-endian;
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1430 pcs1: ethernet-phy@0 {
1436 compatible = "fsl,fman-memac-mdio";
1438 little-endian;
1439 #address-cells = <1>;
1440 #size-cells = <0>;
1443 pcs2: ethernet-phy@0 {
1449 compatible = "fsl,fman-memac-mdio";
1451 little-endian;
1452 #address-cells = <1>;
1453 #size-cells = <0>;
1456 pcs3: ethernet-phy@0 {
1462 compatible = "fsl,fman-memac-mdio";
1464 little-endian;
1465 #address-cells = <1>;
1466 #size-cells = <0>;
1469 pcs4: ethernet-phy@0 {
1475 compatible = "fsl,fman-memac-mdio";
1477 little-endian;
1478 #address-cells = <1>;
1479 #size-cells = <0>;
1482 pcs5: ethernet-phy@0 {
1488 compatible = "fsl,fman-memac-mdio";
1490 little-endian;
1491 #address-cells = <1>;
1492 #size-cells = <0>;
1495 pcs6: ethernet-phy@0 {
1501 compatible = "fsl,fman-memac-mdio";
1503 little-endian;
1504 #address-cells = <1>;
1505 #size-cells = <0>;
1508 pcs7: ethernet-phy@0 {
1514 compatible = "fsl,fman-memac-mdio";
1516 little-endian;
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1521 pcs8: ethernet-phy@0 {
1527 compatible = "fsl,fman-memac-mdio";
1529 little-endian;
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1534 pcs9: ethernet-phy@0 {
1540 compatible = "fsl,fman-memac-mdio";
1542 little-endian;
1543 #address-cells = <1>;
1544 #size-cells = <0>;
1547 pcs10: ethernet-phy@0 {
1553 compatible = "fsl,fman-memac-mdio";
1555 little-endian;
1556 #address-cells = <1>;
1557 #size-cells = <0>;
1560 pcs11: ethernet-phy@0 {
1566 compatible = "fsl,fman-memac-mdio";
1568 little-endian;
1569 #address-cells = <1>;
1570 #size-cells = <0>;
1573 pcs12: ethernet-phy@0 {
1579 compatible = "fsl,fman-memac-mdio";
1581 little-endian;
1582 #address-cells = <1>;
1583 #size-cells = <0>;
1586 pcs13: ethernet-phy@0 {
1592 compatible = "fsl,fman-memac-mdio";
1594 little-endian;
1595 #address-cells = <1>;
1596 #size-cells = <0>;
1599 pcs14: ethernet-phy@0 {
1605 compatible = "fsl,fman-memac-mdio";
1607 little-endian;
1608 #address-cells = <1>;
1609 #size-cells = <0>;
1612 pcs15: ethernet-phy@0 {
1618 compatible = "fsl,fman-memac-mdio";
1620 little-endian;
1621 #address-cells = <1>;
1622 #size-cells = <0>;
1625 pcs16: ethernet-phy@0 {
1631 compatible = "fsl,fman-memac-mdio";
1633 little-endian;
1634 #address-cells = <1>;
1635 #size-cells = <0>;
1638 pcs17: ethernet-phy@0 {
1644 compatible = "fsl,fman-memac-mdio";
1646 little-endian;
1647 #address-cells = <1>;
1648 #size-cells = <0>;
1651 pcs18: ethernet-phy@0 {
1656 fsl_mc: fsl-mc@80c000000 {
1657 compatible = "fsl,qoriq-mc";
1660 msi-parent = <&its>;
1661 /* iommu-map property is fixed up by u-boot */
1662 iommu-map = <0 &smmu 0 0>;
1663 dma-coherent;
1664 #address-cells = <3>;
1665 #size-cells = <1>;
1668 * Region type 0x0 - MC portals
1669 * Region type 0x1 - QBMAN portals
1678 #address-cells = <1>;
1679 #size-cells = <0>;
1682 compatible = "fsl,qoriq-mc-dpmac";
1684 pcs-handle = <&pcs1>;
1688 compatible = "fsl,qoriq-mc-dpmac";
1690 pcs-handle = <&pcs2>;
1694 compatible = "fsl,qoriq-mc-dpmac";
1696 pcs-handle = <&pcs3>;
1700 compatible = "fsl,qoriq-mc-dpmac";
1702 pcs-handle = <&pcs4>;
1706 compatible = "fsl,qoriq-mc-dpmac";
1708 pcs-handle = <&pcs5>;
1712 compatible = "fsl,qoriq-mc-dpmac";
1714 pcs-handle = <&pcs6>;
1718 compatible = "fsl,qoriq-mc-dpmac";
1720 pcs-handle = <&pcs7>;
1724 compatible = "fsl,qoriq-mc-dpmac";
1726 pcs-handle = <&pcs8>;
1730 compatible = "fsl,qoriq-mc-dpmac";
1732 pcs-handle = <&pcs9>;
1736 compatible = "fsl,qoriq-mc-dpmac";
1738 pcs-handle = <&pcs10>;
1742 compatible = "fsl,qoriq-mc-dpmac";
1744 pcs-handle = <&pcs11>;
1748 compatible = "fsl,qoriq-mc-dpmac";
1750 pcs-handle = <&pcs12>;
1754 compatible = "fsl,qoriq-mc-dpmac";
1756 pcs-handle = <&pcs13>;
1760 compatible = "fsl,qoriq-mc-dpmac";
1762 pcs-handle = <&pcs14>;
1766 compatible = "fsl,qoriq-mc-dpmac";
1768 pcs-handle = <&pcs15>;
1772 compatible = "fsl,qoriq-mc-dpmac";
1774 pcs-handle = <&pcs16>;
1778 compatible = "fsl,qoriq-mc-dpmac";
1780 pcs-handle = <&pcs17>;
1784 compatible = "fsl,qoriq-mc-dpmac";
1786 pcs-handle = <&pcs18>;
1794 compatible = "linaro,optee-tz";