Lines Matching +full:0 +full:x3000000
38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
44 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
53 reg = <0x1>;
54 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
63 reg = <0x2>;
64 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
73 reg = <0x3>;
74 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
97 arm,psci-suspend-param = <0x0>;
107 reg = <0x0 0x80000000 0x0 0x0>;
112 #clock-cells = <0>;
120 offset = <0xb0>;
121 mask = <0x02>;
128 thermal-sensors = <&tmu 0>;
239 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
241 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
243 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
245 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
265 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
266 <0x0 0x1420000 0 0x20000>, /* GICC */
267 <0x0 0x1440000 0 0x20000>, /* GICH */
268 <0x0 0x1460000 0 0x20000>; /* GICV */
269 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
278 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
283 reg = <0x0 0x1080000 0x0 0x1000>;
290 reg = <0x0 0x1530000 0x0 0x10000>;
298 #size-cells = <0>;
299 reg = <0x0 0x1550000 0x0 0x10000>,
300 <0x0 0x40000000 0x0 0x10000000>;
313 reg = <0x0 0x1560000 0x0 0x10000>;
324 reg = <0x0 0x1570000 0x0 0x10000>;
328 ranges = <0x0 0x0 0x1570000 0x10000>;
333 #address-cells = <0>;
335 reg = <0x1ac 4>;
337 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
338 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
339 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
340 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
341 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
342 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
343 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
344 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
345 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
346 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
347 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
348 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
349 interrupt-map-mask = <0xf 0x0>;
354 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
355 "fsl,sec-v4.0";
359 ranges = <0x0 0x00 0x1700000 0x100000>;
360 reg = <0x00 0x1700000 0x0 0x100000>;
365 "fsl,sec-v5.0-job-ring",
366 "fsl,sec-v4.0-job-ring";
367 reg = <0x10000 0x10000>;
373 "fsl,sec-v5.0-job-ring",
374 "fsl,sec-v4.0-job-ring";
375 reg = <0x20000 0x10000>;
381 "fsl,sec-v5.0-job-ring",
382 "fsl,sec-v4.0-job-ring";
383 reg = <0x30000 0x10000>;
389 "fsl,sec-v5.0-job-ring",
390 "fsl,sec-v4.0-job-ring";
391 reg = <0x40000 0x10000>;
398 reg = <0x0 0x1880000 0x0 0x10000>;
406 reg = <0x0 0x1890000 0x0 0x10000>;
413 ranges = <0x0 0x5 0x00000000 0x8000000>;
417 ranges = <0x0 0x5 0x08000000 0x8000000>;
422 reg = <0x0 0x1e80000 0x0 0x10000>;
430 reg = <0x0 0x1ee0000 0x0 0x1000>;
436 reg = <0x0 0x1ee1000 0x0 0x1000>;
443 reg = <0x0 0x1f00000 0x0 0x10000>;
444 interrupts = <0 33 0x4>;
445 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
448 <0x00000000 0x00000023>,
449 <0x00000001 0x00000029>,
450 <0x00000002 0x0000002f>,
451 <0x00000003 0x00000036>,
452 <0x00000004 0x0000003c>,
453 <0x00000005 0x00000042>,
454 <0x00000006 0x00000049>,
455 <0x00000007 0x0000004f>,
456 <0x00000008 0x00000055>,
457 <0x00000009 0x0000005c>,
458 <0x0000000a 0x00000062>,
459 <0x0000000b 0x00000068>,
461 <0x00010000 0x00000022>,
462 <0x00010001 0x0000002a>,
463 <0x00010002 0x00000032>,
464 <0x00010003 0x0000003a>,
465 <0x00010004 0x00000042>,
466 <0x00010005 0x0000004a>,
467 <0x00010006 0x00000052>,
468 <0x00010007 0x0000005a>,
469 <0x00010008 0x00000062>,
470 <0x00010009 0x0000006a>,
472 <0x00020000 0x00000021>,
473 <0x00020001 0x0000002b>,
474 <0x00020002 0x00000035>,
475 <0x00020003 0x0000003e>,
476 <0x00020004 0x00000048>,
477 <0x00020005 0x00000052>,
478 <0x00020006 0x0000005c>,
480 <0x00030000 0x00000011>,
481 <0x00030001 0x0000001a>,
482 <0x00030002 0x00000024>,
483 <0x00030003 0x0000002e>,
484 <0x00030004 0x00000038>,
485 <0x00030005 0x00000042>,
486 <0x00030006 0x0000004c>,
487 <0x00030007 0x00000056>;
493 compatible = "fsl,ls1021a-v1.0-dspi";
495 #size-cells = <0>;
496 reg = <0x0 0x2100000 0x0 0x10000>;
509 #size-cells = <0>;
510 reg = <0x0 0x2180000 0x0 0x10000>;
523 #size-cells = <0>;
524 reg = <0x0 0x2190000 0x0 0x10000>;
535 #size-cells = <0>;
536 reg = <0x0 0x21a0000 0x0 0x10000>;
547 #size-cells = <0>;
548 reg = <0x0 0x21b0000 0x0 0x10000>;
558 reg = <0x00 0x21c0500 0x0 0x100>;
567 reg = <0x00 0x21c0600 0x0 0x100>;
576 reg = <0x0 0x21d0500 0x0 0x100>;
585 reg = <0x0 0x21d0600 0x0 0x100>;
594 reg = <0x0 0x2300000 0x0 0x10000>;
604 reg = <0x0 0x2310000 0x0 0x10000>;
614 reg = <0x0 0x2320000 0x0 0x10000>;
624 reg = <0x0 0x2330000 0x0 0x10000>;
634 reg = <0x0 0x2950000 0x0 0x1000>;
644 reg = <0x0 0x2960000 0x0 0x1000>;
654 reg = <0x0 0x2970000 0x0 0x1000>;
664 reg = <0x0 0x2980000 0x0 0x1000>;
674 reg = <0x0 0x2990000 0x0 0x1000>;
684 reg = <0x0 0x29a0000 0x0 0x1000>;
694 reg = <0x0 0x2ad0000 0x0 0x10000>;
704 reg = <0x0 0x2c00000 0x0 0x10000>,
705 <0x0 0x2c10000 0x0 0x10000>,
706 <0x0 0x2c20000 0x0 0x10000>;
724 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
728 reg = <0x0 0x2f00000 0x0 0x10000>;
731 snps,quirk-frame-length-adjustment = <0x20>;
739 reg = <0x0 0x3000000 0x0 0x10000>;
742 snps,quirk-frame-length-adjustment = <0x20>;
750 reg = <0x0 0x3100000 0x0 0x10000>;
753 snps,quirk-frame-length-adjustment = <0x20>;
761 reg = <0x0 0x3200000 0x0 0x10000>,
762 <0x0 0x20140520 0x0 0x4>;
773 reg = <0x0 0x1580000 0x0 0x10000>;
783 reg = <0x0 0x1590000 0x0 0x10000>;
793 reg = <0x0 0x15a0000 0x0 0x10000>;
802 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
803 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
812 bus-range = <0x0 0xff>;
813 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
814 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
817 interrupt-map-mask = <0 0 0 7>;
818 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
819 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
820 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
821 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
828 reg = <0x00 0x03400000 0x0 0x00100000>,
829 <0x40 0x00000000 0x8 0x00000000>;
841 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
842 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
851 bus-range = <0x0 0xff>;
852 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
853 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
856 interrupt-map-mask = <0 0 0 7>;
857 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
858 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
859 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
860 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
867 reg = <0x00 0x03500000 0x0 0x00100000>,
868 <0x48 0x00000000 0x8 0x00000000>;
880 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
881 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
890 bus-range = <0x0 0xff>;
891 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
892 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
895 interrupt-map-mask = <0 0 0 7>;
896 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
897 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
898 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
899 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
906 reg = <0x00 0x03600000 0x0 0x00100000>,
907 <0x50 0x00000000 0x8 0x00000000>;
919 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
920 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
921 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
931 block-offset = <0x10000>;
940 reg = <0x0 0x1ee2140 0x0 0x4>;
946 reg = <0x0 0x29d0000 0x0 0x10000>;
947 fsl,rcpm-wakeup = <&rcpm 0x20000>;
960 size = <0 0x1000000>;
961 alignment = <0 0x1000000>;
967 size = <0 0x800000>;
968 alignment = <0 0x800000>;
974 size = <0 0x2000000>;
975 alignment = <0 0x2000000>;