Lines Matching +full:0 +full:x3000000
37 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0>;
49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
58 reg = <0x1>;
59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
68 reg = <0x2>;
69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
78 reg = <0x3>;
79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
102 arm,psci-suspend-param = <0x0>;
111 reg = <0x0 0x80000000 0 0x80000000>;
122 size = <0 0x1000000>;
123 alignment = <0 0x1000000>;
129 size = <0 0x400000>;
130 alignment = <0 0x400000>;
136 size = <0 0x2000000>;
137 alignment = <0 0x2000000>;
144 #clock-cells = <0>;
152 offset = <0xb0>;
153 mask = <0x02>;
160 thermal-sensors = <&tmu 0>;
271 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
272 <1 14 0xf08>, /* Physical Non-Secure PPI */
273 <1 11 0xf08>, /* Virtual PPI */
274 <1 10 0xf08>; /* Hypervisor PPI */
280 interrupts = <0 106 0x4>,
281 <0 107 0x4>,
282 <0 95 0x4>,
283 <0 97 0x4>;
294 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
295 <0x0 0x1402000 0 0x2000>, /* GICC */
296 <0x0 0x1404000 0 0x2000>, /* GICH */
297 <0x0 0x1406000 0 0x2000>; /* GICV */
298 interrupts = <1 9 0xf08>;
306 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
311 reg = <0x0 0x1ee1000 0x0 0x1000>;
318 reg = <0x0 0x1570000 0x0 0x10000>;
322 ranges = <0x0 0x0 0x1570000 0x10000>;
327 #address-cells = <0>;
329 reg = <0x1ac 4>;
331 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
332 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
333 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
334 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
335 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
336 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
337 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
338 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
339 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
340 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
341 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
342 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
343 interrupt-map-mask = <0xf 0x0>;
348 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
349 "fsl,sec-v4.0";
353 ranges = <0x0 0x00 0x1700000 0x100000>;
354 reg = <0x00 0x1700000 0x0 0x100000>;
355 interrupts = <0 75 0x4>;
360 "fsl,sec-v5.0-job-ring",
361 "fsl,sec-v4.0-job-ring";
362 reg = <0x10000 0x10000>;
363 interrupts = <0 71 0x4>;
368 "fsl,sec-v5.0-job-ring",
369 "fsl,sec-v4.0-job-ring";
370 reg = <0x20000 0x10000>;
371 interrupts = <0 72 0x4>;
376 "fsl,sec-v5.0-job-ring",
377 "fsl,sec-v4.0-job-ring";
378 reg = <0x30000 0x10000>;
379 interrupts = <0 73 0x4>;
384 "fsl,sec-v5.0-job-ring",
385 "fsl,sec-v4.0-job-ring";
386 reg = <0x40000 0x10000>;
387 interrupts = <0 74 0x4>;
393 reg = <0x0 0x1e80000 0x0 0x10000>;
401 reg = <0x0 0x1ee0000 0x0 0x1000>;
407 reg = <0x0 0x1530000 0x0 0x10000>;
408 interrupts = <0 43 0x4>;
414 #size-cells = <0>;
415 reg = <0x0 0x1550000 0x0 0x10000>,
416 <0x0 0x40000000 0x0 0x4000000>;
418 interrupts = <0 99 0x4>;
429 reg = <0x0 0x1560000 0x0 0x10000>;
430 interrupts = <0 62 0x4>;
431 clock-frequency = <0>;
440 reg = <0x0 0x1080000 0x0 0x1000>;
441 interrupts = <0 144 0x4>;
447 reg = <0x0 0x1f00000 0x0 0x10000>;
448 interrupts = <0 33 0x4>;
449 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
451 <0x00000000 0x00000023>,
452 <0x00000001 0x0000002a>,
453 <0x00000002 0x00000031>,
454 <0x00000003 0x00000037>,
455 <0x00000004 0x0000003e>,
456 <0x00000005 0x00000044>,
457 <0x00000006 0x0000004b>,
458 <0x00000007 0x00000051>,
459 <0x00000008 0x00000058>,
460 <0x00000009 0x0000005e>,
461 <0x0000000a 0x00000065>,
462 <0x0000000b 0x0000006b>,
464 <0x00010000 0x00000023>,
465 <0x00010001 0x0000002b>,
466 <0x00010002 0x00000033>,
467 <0x00010003 0x0000003b>,
468 <0x00010004 0x00000043>,
469 <0x00010005 0x0000004b>,
470 <0x00010006 0x00000054>,
471 <0x00010007 0x0000005c>,
472 <0x00010008 0x00000064>,
473 <0x00010009 0x0000006c>,
475 <0x00020000 0x00000021>,
476 <0x00020001 0x0000002c>,
477 <0x00020002 0x00000036>,
478 <0x00020003 0x00000040>,
479 <0x00020004 0x0000004b>,
480 <0x00020005 0x00000055>,
481 <0x00020006 0x0000005f>,
483 <0x00030000 0x00000013>,
484 <0x00030001 0x0000001d>,
485 <0x00030002 0x00000028>,
486 <0x00030003 0x00000032>,
487 <0x00030004 0x0000003d>,
488 <0x00030005 0x00000047>,
489 <0x00030006 0x00000052>,
490 <0x00030007 0x0000005c>;
496 reg = <0x0 0x1880000 0x0 0x10000>;
503 reg = <0x0 0x1890000 0x0 0x10000>;
509 ranges = <0x0 0x5 0x08000000 0x8000000>;
513 ranges = <0x0 0x5 0x00000000 0x8000000>;
517 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
519 #size-cells = <0>;
520 reg = <0x0 0x2100000 0x0 0x10000>;
521 interrupts = <0 64 0x4>;
533 #size-cells = <0>;
534 reg = <0x0 0x2180000 0x0 0x10000>;
535 interrupts = <0 56 0x4>;
548 #size-cells = <0>;
549 reg = <0x0 0x2190000 0x0 0x10000>;
550 interrupts = <0 57 0x4>;
561 #size-cells = <0>;
562 reg = <0x0 0x21a0000 0x0 0x10000>;
563 interrupts = <0 58 0x4>;
574 #size-cells = <0>;
575 reg = <0x0 0x21b0000 0x0 0x10000>;
576 interrupts = <0 59 0x4>;
586 reg = <0x00 0x21c0500 0x0 0x100>;
587 interrupts = <0 54 0x4>;
594 reg = <0x00 0x21c0600 0x0 0x100>;
595 interrupts = <0 54 0x4>;
602 reg = <0x0 0x21d0500 0x0 0x100>;
603 interrupts = <0 55 0x4>;
610 reg = <0x0 0x21d0600 0x0 0x100>;
611 interrupts = <0 55 0x4>;
618 reg = <0x0 0x2300000 0x0 0x10000>;
619 interrupts = <0 66 0x4>;
628 reg = <0x0 0x2310000 0x0 0x10000>;
629 interrupts = <0 67 0x4>;
638 reg = <0x0 0x2320000 0x0 0x10000>;
639 interrupts = <0 68 0x4>;
648 reg = <0x0 0x2330000 0x0 0x10000>;
649 interrupts = <0 134 0x4>;
660 ranges = <0x0 0x0 0x2400000 0x40000>;
661 reg = <0x0 0x2400000 0x0 0x480>;
669 reg = <0x80 0x80>;
670 #address-cells = <0>;
679 #size-cells = <0>;
682 reg = <0x700 0x80>;
690 reg = <0x1000 0x800>;
695 reg = <0x2000 0x200>;
702 reg = <0x2200 0x200>;
711 ranges = <0x0 0x10000 0x6000>;
713 data-only@0 {
716 reg = <0x0 0x6000>;
723 reg = <0x0 0x2950000 0x0 0x1000>;
724 interrupts = <0 48 0x4>;
725 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>;
732 reg = <0x0 0x2960000 0x0 0x1000>;
733 interrupts = <0 49 0x4>;
742 reg = <0x0 0x2970000 0x0 0x1000>;
743 interrupts = <0 50 0x4>;
752 reg = <0x0 0x2980000 0x0 0x1000>;
753 interrupts = <0 51 0x4>;
762 reg = <0x0 0x2990000 0x0 0x1000>;
763 interrupts = <0 52 0x4>;
772 reg = <0x0 0x29a0000 0x0 0x1000>;
773 interrupts = <0 53 0x4>;
782 reg = <0x0 0x2ad0000 0x0 0x10000>;
783 interrupts = <0 83 0x4>;
793 reg = <0x0 0x2c00000 0x0 0x10000>,
794 <0x0 0x2c10000 0x0 0x10000>,
795 <0x0 0x2c20000 0x0 0x10000>;
796 interrupts = <0 103 0x4>,
797 <0 103 0x4>;
813 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
817 reg = <0x0 0x2f00000 0x0 0x10000>;
818 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
820 snps,quirk-frame-length-adjustment = <0x20>;
829 reg = <0x0 0x3000000 0x0 0x10000>;
830 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
832 snps,quirk-frame-length-adjustment = <0x20>;
841 reg = <0x0 0x3100000 0x0 0x10000>;
842 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
844 snps,quirk-frame-length-adjustment = <0x20>;
853 reg = <0x0 0x3200000 0x0 0x10000>,
854 <0x0 0x20140520 0x0 0x4>;
856 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
865 reg = <0x0 0x1571000 0x0 0x8>;
867 interrupts = <0 116 0x4>;
872 reg = <0x0 0x1572000 0x0 0x8>;
874 interrupts = <0 126 0x4>;
879 reg = <0x0 0x1573000 0x0 0x8>;
881 interrupts = <0 160 0x4>;
886 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
887 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
889 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>,
890 <0 118 IRQ_TYPE_LEVEL_HIGH>;
896 bus-range = <0x0 0xff>;
897 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
898 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
901 interrupt-map-mask = <0 0 0 7>;
902 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
903 <0000 0 0 2 &gic 0 111 0x4>,
904 <0000 0 0 3 &gic 0 112 0x4>,
905 <0000 0 0 4 &gic 0 113 0x4>;
906 fsl,pcie-scfg = <&scfg 0>;
913 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
914 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
916 interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>,
917 <0 128 IRQ_TYPE_LEVEL_HIGH>;
923 bus-range = <0x0 0xff>;
924 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
925 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
928 interrupt-map-mask = <0 0 0 7>;
929 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
930 <0000 0 0 2 &gic 0 121 0x4>,
931 <0000 0 0 3 &gic 0 122 0x4>,
932 <0000 0 0 4 &gic 0 123 0x4>;
940 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
941 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
943 interrupts = <0 161 IRQ_TYPE_LEVEL_HIGH>,
944 <0 162 IRQ_TYPE_LEVEL_HIGH>;
950 bus-range = <0x0 0xff>;
951 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
952 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
955 interrupt-map-mask = <0 0 0 7>;
956 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
957 <0000 0 0 2 &gic 0 155 0x4>,
958 <0000 0 0 3 &gic 0 156 0x4>,
959 <0000 0 0 4 &gic 0 157 0x4>;
967 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
968 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
969 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
979 block-offset = <0x10000>;
988 reg = <0x0 0x1ee2140 0x0 0x4>;
994 reg = <0x0 0x29d0000 0x0 0x10000>;
995 fsl,rcpm-wakeup = <&rcpm 0x20000>;