Lines Matching +full:ifc +full:- +full:nand

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5  * Copyright 2014-2015 Freescale Semiconductor, Inc.
6  * Copyright 2018-2021 NXP
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 	compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
27 		sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
28 		sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
29 		sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
30 		sgmii-riser-s4-p1 = &sgmii_phy_s4_p1;
31 		qsgmii-s1-p1 = &qsgmii_phy_s1_p1;
32 		qsgmii-s1-p2 = &qsgmii_phy_s1_p2;
33 		qsgmii-s1-p3 = &qsgmii_phy_s1_p3;
34 		qsgmii-s1-p4 = &qsgmii_phy_s1_p4;
35 		qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
36 		qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
37 		qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
38 		qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
39 		emi1-slot1 = &ls1043mdio_s1;
40 		emi1-slot2 = &ls1043mdio_s2;
41 		emi1-slot3 = &ls1043mdio_s3;
42 		emi1-slot4 = &ls1043mdio_s4;
46 		stdout-path = "serial0:115200n8";
58 &ifc {
59 	#address-cells = <2>;
60 	#size-cells = <1>;
61 	/* NOR, NAND Flashes and FPGA on board */
68 		compatible = "cfi-flash";
70 		big-endian;
71 		bank-width = <2>;
72 		device-width = <1>;
75 	nand@1,0 {
76 		compatible = "fsl,ifc-nand";
80 	fpga: board-control@2,0 {
81 		compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
83 		#address-cells = <1>;
84 		#size-cells = <1>;
92 	i2c-mux@77 {
95 		#address-cells = <1>;
96 		#size-cells = <0>;
99 			#address-cells = <1>;
100 			#size-cells = <0>;
112 			#address-cells = <1>;
113 			#size-cells = <0>;
119 				shunt-resistor = <1000>;
125 				shunt-resistor = <1000>;
130 			#address-cells = <1>;
131 			#size-cells = <0>;
144 			temp-sensor@4c {
161 		#address-cells = <1>;
162 		#size-cells = <1>;
163 		spi-max-frequency = <20000000>;
164 		spi-rx-bus-width = <4>;
165 		spi-tx-bus-width = <4>;
174 #include "fsl-ls1043-post.dtsi"
178 		phy-handle = <&qsgmii_phy_s2_p1>;
179 		phy-connection-type = "sgmii";
183 		phy-handle = <&qsgmii_phy_s2_p2>;
184 		phy-connection-type = "sgmii";
188 		phy-handle = <&rgmii_phy1>;
189 		phy-connection-type = "rgmii";
193 		phy-handle = <&rgmii_phy2>;
194 		phy-connection-type = "rgmii";
198 		phy-handle = <&qsgmii_phy_s2_p3>;
199 		phy-connection-type = "sgmii";
203 		phy-handle = <&qsgmii_phy_s2_p4>;
204 		phy-connection-type = "sgmii";
208 		fixed-link = <1 1 10000 0 0>;
209 		phy-connection-type = "xgmii";
214 	mdio-mux-emi1@54 {
215 		compatible = "mdio-mux-mmioreg", "mdio-mux";
216 		mdio-parent-bus = <&mdio0>;
217 		#address-cells = <1>;
218 		#size-cells = <0>;
220 		mux-mask = <0xe0>; /* EMI1 */
222 		/* On-board RGMII1 PHY */
225 			#address-cells = <1>;
226 			#size-cells = <0>;
228 			rgmii_phy1: ethernet-phy@1 { /* MAC3 */
233 		/* On-board RGMII2 PHY */
236 			#address-cells = <1>;
237 			#size-cells = <0>;
239 			rgmii_phy2: ethernet-phy@2 { /* MAC4 */
247 			#address-cells = <1>;
248 			#size-cells = <0>;
251 			qsgmii_phy_s1_p1: ethernet-phy@4 {
255 			qsgmii_phy_s1_p2: ethernet-phy@5 {
259 			qsgmii_phy_s1_p3: ethernet-phy@6 {
263 			qsgmii_phy_s1_p4: ethernet-phy@7 {
267 			sgmii_phy_s1_p1: ethernet-phy@1c {
275 			#address-cells = <1>;
276 			#size-cells = <0>;
279 			qsgmii_phy_s2_p1: ethernet-phy@8 {
283 			qsgmii_phy_s2_p2: ethernet-phy@9 {
287 			qsgmii_phy_s2_p3: ethernet-phy@a {
291 			qsgmii_phy_s2_p4: ethernet-phy@b {
295 			sgmii_phy_s2_p1: ethernet-phy@1c {
303 			#address-cells = <1>;
304 			#size-cells = <0>;
307 			sgmii_phy_s3_p1: ethernet-phy@1c {
315 			#address-cells = <1>;
316 			#size-cells = <0>;
319 			sgmii_phy_s4_p1: ethernet-phy@1c {