Lines Matching +full:1 +full:e80000
31 #address-cells = <1>;
77 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
78 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
79 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
80 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
96 interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
145 #address-cells = <1>;
153 QORIQ_CLK_PLL_DIV(1)>,
155 QORIQ_CLK_PLL_DIV(1)>;
164 QORIQ_CLK_PLL_DIV(1)>;
183 QORIQ_CLK_PLL_DIV(1)>;
196 #address-cells = <1>;
197 #size-cells = <1>;
239 #address-cells = <1>;
240 #size-cells = <1>;
274 sfp: efuse@1e80000 {
282 sec_mon: sec_mon@1e90000 {
290 dcfg: dcfg@1ee0000 {
297 clockgen: clocking@1ee1000 {
305 tmu: tmu@1f00000 {
350 #thermal-sensor-cells = <1>;
355 #address-cells = <1>;
366 #address-cells = <1>;
377 #address-cells = <1>;
383 QORIQ_CLK_PLL_DIV(1)>;
394 QORIQ_CLK_PLL_DIV(1)>;
403 QORIQ_CLK_PLL_DIV(1)>;
432 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>;
451 dmas = <&edma0 1 47>,
452 <&edma0 1 46>;
471 dmas = <&edma0 1 45>,
472 <&edma0 1 44>;
501 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
511 QORIQ_CLK_PLL_DIV(1)>;
547 #interrupt-cells = <1>;
549 interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
556 rcpm: power-controller@1ee2140 {
559 #fsl,rcpm-wakeup-cells = <1>;