Lines Matching +full:cpu +full:- +full:syscon
1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov920.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,exynos-usi.h>
15 #address-cells = <2>;
16 #size-cells = <1>;
18 interrupt-parent = <&gic>;
31 arm-pmu {
32 compatible = "arm,cortex-a78-pmu";
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-output-names = "oscclk";
43 #address-cells = <2>;
44 #size-cells = <0>;
46 cpu-map {
49 cpu = <&cpu0>;
52 cpu = <&cpu1>;
55 cpu = <&cpu2>;
58 cpu = <&cpu3>;
64 cpu = <&cpu4>;
67 cpu = <&cpu5>;
70 cpu = <&cpu6>;
73 cpu = <&cpu7>;
79 cpu = <&cpu8>;
82 cpu = <&cpu9>;
87 cpu0: cpu@0 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a78ae";
91 enable-method = "psci";
94 cpu1: cpu@100 {
95 device_type = "cpu";
96 compatible = "arm,cortex-a78ae";
98 enable-method = "psci";
101 cpu2: cpu@200 {
102 device_type = "cpu";
103 compatible = "arm,cortex-a78ae";
105 enable-method = "psci";
108 cpu3: cpu@300 {
109 device_type = "cpu";
110 compatible = "arm,cortex-a78ae";
112 enable-method = "psci";
115 cpu4: cpu@10000 {
116 device_type = "cpu";
117 compatible = "arm,cortex-a78ae";
119 enable-method = "psci";
122 cpu5: cpu@10100 {
123 device_type = "cpu";
124 compatible = "arm,cortex-a78ae";
126 enable-method = "psci";
129 cpu6: cpu@10200 {
130 device_type = "cpu";
131 compatible = "arm,cortex-a78ae";
133 enable-method = "psci";
136 cpu7: cpu@10300 {
137 device_type = "cpu";
138 compatible = "arm,cortex-a78ae";
140 enable-method = "psci";
143 cpu8: cpu@20000 {
144 device_type = "cpu";
145 compatible = "arm,cortex-a78ae";
147 enable-method = "psci";
150 cpu9: cpu@20100 {
151 device_type = "cpu";
152 compatible = "arm,cortex-a78ae";
154 enable-method = "psci";
159 compatible = "arm,psci-1.0";
164 compatible = "simple-bus";
165 #address-cells = <1>;
166 #size-cells = <1>;
170 compatible = "samsung,exynosautov920-chipid",
171 "samsung,exynos850-chipid";
175 gic: interrupt-controller@10400000 {
176 compatible = "arm,gic-v3";
177 #interrupt-cells = <3>;
178 #address-cells = <0>;
179 interrupt-controller;
185 cmu_peric0: clock-controller@10800000 {
186 compatible = "samsung,exynosautov920-cmu-peric0";
188 #clock-cells = <1>;
193 clock-names = "oscclk",
198 syscon_peric0: syscon@10820000 {
199 compatible = "samsung,exynosautov920-peric0-sysreg",
200 "syscon";
205 compatible = "samsung,exynosautov920-pinctrl";
211 compatible = "samsung,exynosautov920-usi",
212 "samsung,exynos850-usi";
216 #address-cells = <1>;
217 #size-cells = <1>;
221 clock-names = "pclk", "ipclk";
225 compatible = "samsung,exynosautov920-uart",
226 "samsung,exynos850-uart";
229 pinctrl-names = "default";
230 pinctrl-0 = <&uart0_bus>;
233 clock-names = "uart", "clk_uart_baud0";
234 samsung,uart-fifosize = <256>;
240 compatible = "samsung,exynosautov920-pwm",
241 "samsung,exynos4210-pwm";
243 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
244 #pwm-cells = <3>;
246 clock-names = "timers";
250 syscon_peric1: syscon@10c20000 {
251 compatible = "samsung,exynosautov920-peric1-sysreg",
252 "syscon";
257 compatible = "samsung,exynosautov920-pinctrl";
262 cmu_top: clock-controller@11000000 {
263 compatible = "samsung,exynosautov920-cmu-top";
265 #clock-cells = <1>;
268 clock-names = "oscclk";
272 compatible = "samsung,exynosautov920-pinctrl";
275 wakeup-interrupt-controller {
276 compatible = "samsung,exynosautov920-wakeup-eint";
280 pmu_system_controller: system-controller@11860000 {
281 compatible = "samsung,exynosautov920-pmu",
282 "samsung,exynos7-pmu","syscon";
287 compatible = "samsung,exynosautov920-pinctrl";
293 compatible = "samsung,exynosautov920-pinctrl";
299 compatible = "samsung,exynosautov920-pinctrl";
305 compatible = "samsung,exynosautov920-pinctrl";
311 compatible = "samsung,exynosautov920-pinctrl";
317 compatible = "arm,armv8-timer";
326 #include "exynosautov920-pinctrl.dtsi"